102 lines
5.3 KiB
C
102 lines
5.3 KiB
C
/*
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* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* This file is derivative of CMSIS V5.00 ARMCM3.h
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*/
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#ifndef CMSDK_BEETLE_H
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#define CMSDK_BEETLE_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ------------------------- Interrupt Number Definition ------------------------ */
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typedef enum IRQn
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{
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/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
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NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
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HardFault_IRQn = -13, /* 3 HardFault Interrupt */
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MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
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BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
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SVCall_IRQn = -5, /* 11 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
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SysTick_IRQn = -1, /* 15 System Tick Interrupt */
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/* --------------------- CMSDK_BEETLE Specific Interrupt Numbers ---------------- */
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UART0_IRQn = 0, /* UART 0 RX and TX Combined Interrupt */
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Spare_IRQn = 1, /* Undefined */
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UART1_IRQn = 2, /* UART 1 RX and TX Combined Interrupt */
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I2C0_IRQn = 3, /* I2C 0 Interrupt */
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I2C1_IRQn = 4, /* I2C 1 Interrupt */
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RTC_IRQn = 5, /* RTC Interrupt */
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PORT0_ALL_IRQn = 6, /* GPIO Port 0 combined Interrupt */
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PORT1_ALL_IRQn = 7, /* GPIO Port 1 combined Interrupt */
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TIMER0_IRQn = 8, /* TIMER 0 Interrupt */
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TIMER1_IRQn = 9, /* TIMER 1 Interrupt */
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DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */
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SPI0_IRQn = 11, /* SPI 0 Interrupt */
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UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */
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SPI1_IRQn = 13, /* SPI 1 Interrupt */
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QSPI_IRQn = 14, /* QUAD SPI Interrupt */
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DMA_IRQn = 15, /* Reserved for DMA Interrupt */
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PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */
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PORT0_1_IRQn = 17, /* There are 16 pins in total */
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PORT0_2_IRQn = 18,
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PORT0_3_IRQn = 19,
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PORT0_4_IRQn = 20,
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PORT0_5_IRQn = 21,
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PORT0_6_IRQn = 22,
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PORT0_7_IRQn = 23,
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PORT0_8_IRQn = 24,
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PORT0_9_IRQn = 25,
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PORT0_10_IRQn = 26,
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PORT0_11_IRQn = 27,
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PORT0_12_IRQn = 28,
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PORT0_13_IRQn = 29,
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PORT0_14_IRQn = 30,
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PORT0_15_IRQn = 31,
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SYSERROR_IRQn = 32, /* System Error Interrupt */
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EFLASH_IRQn = 33, /* Embedded Flash Interrupt */
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LLCC_TXCMD_EMPTY_IRQn = 34, /* t.b.a */
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LLCC_TXEVT_EMPTY_IRQn = 35, /* t.b.a */
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LLCC_TXDMAH_DONE_IRQn = 36, /* t.b.a */
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LLCC_TXDMAL_DONE_IRQn = 37, /* t.b.a */
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LLCC_RXCMD_VALID_IRQn = 38, /* t.b.a */
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LLCC_RXEVT_VALID_IRQn = 39, /* t.b.a */
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LLCC_RXDMAH_DONE_IRQn = 40, /* t.b.a */
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LLCC_RXDMAL_DONE_IRQn = 41, /* t.b.a */
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PORT2_ALL_IRQn = 42, /* GPIO Port 2 combined Interrupt */
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PORT3_ALL_IRQn = 43, /* GPIO Port 3 combined Interrupt */
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TRNG_IRQn = 44, /* Random number generator Interrupt */
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} IRQn_Type;
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/* ================================================================================ */
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/* ================ Processor and Core Peripheral Section ================ */
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/* ================================================================================ */
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/* -------- Configuration of the Cortex-M3 Processor and Core Peripherals ------- */
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#define __CM3_REV 0x0201U /* Core revision r2p1 */
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#define __MPU_PRESENT 1 /* MPU present */
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#define __VTOR_PRESENT 1 /* VTOR present or not */
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#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
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#ifdef __cplusplus
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}
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#endif
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#include <core_cm3.h> /* Processor and core peripherals */
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#endif /* CMSDK_BEETLE_H */
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