64 lines
1.2 KiB
ArmAsm
64 lines
1.2 KiB
ArmAsm
/*
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* Copyright (c) 2021 Andes Technology Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc_v5.h"
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#include <zephyr/toolchain.h>
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/* exports */
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GTEXT(entry)
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SECTION_FUNC(init, entry)
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/* Disable linker relaxation before GP register initialization. */
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.option push
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.option norelax
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#ifdef CONFIG_SOC_ANDES_V5_EXECIT
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/* Initialize EXECIT table */
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la t0, _ITB_BASE_
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csrw NDS_UITB, t0
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#endif
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#ifdef CONFIG_ICACHE
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/* Enable I cache with HW prefetcher. */
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li t0, (1 << 9) | (1 << 0)
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csrs NDS_MCACHE_CTL, t0
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#endif
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#ifdef CONFIG_DCACHE
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/*
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* Enable D cache with HW prefetcher, D-cache write-around
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* (threshold: 4 cache lines), and CM (Coherence Manager).
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*/
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li t0, (0x3 << 13)
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csrc NDS_MCACHE_CTL, t0
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li t0, (1 << 19) | (1 << 13) | (1 << 10) | (1 << 1)
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csrs NDS_MCACHE_CTL, t0
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/* Check if CPU support CM or not. */
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csrr t0, NDS_MCACHE_CTL
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li t1, (1 << 19)
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and t0, t0, t1
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beqz t0, cache_enable_finish
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/* If CPU support CM, check if CM is enabled. */
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li t1, (1 << 20)
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check_cm_enabled:
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csrr t0, NDS_MCACHE_CTL
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and t0, t0, t1
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beqz t0, check_cm_enabled
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cache_enable_finish:
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#endif
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/* Enable misaligned access and non-blocking load */
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li t0, (1 << 8) | (1 << 6)
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csrs NDS_MMISC_CTL, t0
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j __start
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.option pop
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