228 lines
7.8 KiB
C
228 lines
7.8 KiB
C
/*
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* Copyright 2023-2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_s32_wkpu
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/irq.h>
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#include <zephyr/sys/sys_io.h>
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#include <zephyr/sys/math_extras.h>
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#include <zephyr/drivers/interrupt_controller/intc_wkpu_nxp_s32.h>
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/* NMI Status Flag Register */
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#define WKPU_NSR 0x0
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/* NMI Configuration Register */
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#define WKPU_NCR 0x8
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/* Wakeup/Interrupt Status Flag Register */
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#define WKPU_WISR(n) (0x14 + 0x40 * (n))
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/* Interrupt Request Enable Register */
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#define WKPU_IRER(n) (0x18 + 0x40 * (n))
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/* Wakeup Request Enable Register */
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#define WKPU_WRER(n) (0x1c + 0x40 * (n))
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/* Wakeup/Interrupt Rising-Edge Event Enable Register */
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#define WKPU_WIREER(n) (0x28 + 0x40 * (n))
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/* Wakeup/Interrupt Falling-Edge Event Enable Register */
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#define WKPU_WIFEER(n) (0x2c + 0x40 * (n))
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/* Wakeup/Interrupt Filter Enable Register */
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#define WKPU_WIFER(n) (0x30 + 0x40 * (n))
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/* Handy accessors */
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#define REG_READ(r) sys_read32(config->base + (r))
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#define REG_WRITE(r, v) sys_write32((v), config->base + (r))
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struct wkpu_nxp_s32_config {
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mem_addr_t base;
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uint64_t filter_enable;
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};
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struct wkpu_nxp_s32_cb {
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wkpu_nxp_s32_callback_t cb;
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uint8_t pin;
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void *data;
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};
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struct wkpu_nxp_s32_data {
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struct wkpu_nxp_s32_cb *cb;
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};
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static void wkpu_nxp_s32_interrupt_handler(const struct device *dev)
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{
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const struct wkpu_nxp_s32_config *config = dev->config;
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struct wkpu_nxp_s32_data *data = dev->data;
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uint64_t pending = wkpu_nxp_s32_get_pending(dev);
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uint64_t irq_mask;
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int irq;
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while (pending) {
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irq_mask = LSB_GET(pending);
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irq = u64_count_trailing_zeros(irq_mask);
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/* Clear status flag */
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REG_WRITE(WKPU_WISR(irq / 32U), REG_READ(WKPU_WISR(irq / 32U)) | irq_mask);
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if (data->cb[irq].cb != NULL) {
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data->cb[irq].cb(data->cb[irq].pin, data->cb[irq].data);
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}
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pending ^= irq_mask;
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}
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}
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int wkpu_nxp_s32_set_callback(const struct device *dev, uint8_t irq, uint8_t pin,
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wkpu_nxp_s32_callback_t cb, void *arg)
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{
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struct wkpu_nxp_s32_data *data = dev->data;
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__ASSERT_NO_MSG(irq < CONFIG_NXP_S32_WKPU_SOURCES_MAX);
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if ((data->cb[irq].cb == cb) && (data->cb[irq].data == arg)) {
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return 0;
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}
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if (data->cb[irq].cb) {
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return -EBUSY;
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}
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data->cb[irq].cb = cb;
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data->cb[irq].pin = pin;
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data->cb[irq].data = arg;
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return 0;
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}
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void wkpu_nxp_s32_unset_callback(const struct device *dev, uint8_t irq)
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{
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struct wkpu_nxp_s32_data *data = dev->data;
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__ASSERT_NO_MSG(irq < CONFIG_NXP_S32_WKPU_SOURCES_MAX);
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data->cb[irq].cb = NULL;
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data->cb[irq].pin = 0;
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data->cb[irq].data = NULL;
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}
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void wkpu_nxp_s32_enable_interrupt(const struct device *dev, uint8_t irq,
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enum wkpu_nxp_s32_trigger trigger)
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{
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const struct wkpu_nxp_s32_config *config = dev->config;
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uint32_t mask = BIT(irq % 32U);
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uint8_t reg_idx = irq / 32U;
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uint32_t reg_val;
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__ASSERT_NO_MSG(irq < CONFIG_NXP_S32_WKPU_SOURCES_MAX);
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/* Configure trigger */
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reg_val = REG_READ(WKPU_WIREER(reg_idx));
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if ((trigger == WKPU_NXP_S32_RISING_EDGE) || (trigger == WKPU_NXP_S32_BOTH_EDGES)) {
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reg_val |= mask;
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} else {
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reg_val &= ~mask;
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}
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REG_WRITE(WKPU_WIREER(reg_idx), reg_val);
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reg_val = REG_READ(WKPU_WIFEER(reg_idx));
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if ((trigger == WKPU_NXP_S32_FALLING_EDGE) || (trigger == WKPU_NXP_S32_BOTH_EDGES)) {
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reg_val |= mask;
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} else {
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reg_val &= ~mask;
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}
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REG_WRITE(WKPU_WIFEER(reg_idx), reg_val);
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/* Clear status flag and unmask interrupt */
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REG_WRITE(WKPU_WISR(reg_idx), REG_READ(WKPU_WISR(reg_idx)) | mask);
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REG_WRITE(WKPU_IRER(reg_idx), REG_READ(WKPU_IRER(reg_idx)) | mask);
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}
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void wkpu_nxp_s32_disable_interrupt(const struct device *dev, uint8_t irq)
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{
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const struct wkpu_nxp_s32_config *config = dev->config;
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uint32_t mask = BIT(irq % 32U);
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uint8_t reg_idx = irq / 32U;
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__ASSERT_NO_MSG(irq < CONFIG_NXP_S32_WKPU_SOURCES_MAX);
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/* Disable triggers */
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REG_WRITE(WKPU_WIREER(reg_idx), REG_READ(WKPU_WIREER(reg_idx)) & ~mask);
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REG_WRITE(WKPU_WIFEER(reg_idx), REG_READ(WKPU_WIFEER(reg_idx)) & ~mask);
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/* Clear status flag and mask interrupt */
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REG_WRITE(WKPU_WISR(reg_idx), REG_READ(WKPU_WISR(reg_idx)) | mask);
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REG_WRITE(WKPU_IRER(reg_idx), REG_READ(WKPU_IRER(reg_idx)) & ~mask);
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}
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uint64_t wkpu_nxp_s32_get_pending(const struct device *dev)
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{
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const struct wkpu_nxp_s32_config *config = dev->config;
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uint64_t flags;
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flags = REG_READ(WKPU_WISR(0U)) & REG_READ(WKPU_IRER(0U));
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if (CONFIG_NXP_S32_WKPU_SOURCES_MAX > 32U) {
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flags |= ((uint64_t)(REG_READ(WKPU_WISR(1U)) & REG_READ(WKPU_IRER(1U)))) << 32U;
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}
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return flags;
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}
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static int wkpu_nxp_s32_init(const struct device *dev)
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{
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const struct wkpu_nxp_s32_config *config = dev->config;
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/* Disable triggers, clear status flags and mask all interrupts */
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REG_WRITE(WKPU_WIREER(0U), 0U);
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REG_WRITE(WKPU_WIFEER(0U), 0U);
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REG_WRITE(WKPU_WISR(0U), 0xffffffff);
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REG_WRITE(WKPU_IRER(0U), 0U);
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/* Configure glitch filters */
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REG_WRITE(WKPU_WIFER(0U), (uint32_t)config->filter_enable);
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if (CONFIG_NXP_S32_WKPU_SOURCES_MAX > 32U) {
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REG_WRITE(WKPU_WIREER(1U), 0U);
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REG_WRITE(WKPU_WIFEER(1U), 0U);
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REG_WRITE(WKPU_WISR(1U), 0xffffffff);
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REG_WRITE(WKPU_IRER(1U), 0U);
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REG_WRITE(WKPU_WIFER(1U), (uint32_t)(config->filter_enable >> 32U));
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}
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return 0;
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}
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#define WKPU_NXP_S32_FILTER_CONFIG(idx, n) \
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COND_CODE_1(DT_PROP(DT_INST_CHILD(n, irq_##idx), filter_enable), (BIT(idx)), (0U))
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#define WKPU_NXP_S32_INIT_DEVICE(n) \
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static const struct wkpu_nxp_s32_config wkpu_nxp_s32_conf_##n = { \
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.base = DT_INST_REG_ADDR(n), \
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.filter_enable = LISTIFY(CONFIG_NXP_S32_WKPU_SOURCES_MAX, \
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WKPU_NXP_S32_FILTER_CONFIG, (|), n), \
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}; \
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static struct wkpu_nxp_s32_cb wkpu_nxp_s32_cb_##n[CONFIG_NXP_S32_WKPU_SOURCES_MAX]; \
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static struct wkpu_nxp_s32_data wkpu_nxp_s32_data_##n = { \
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.cb = wkpu_nxp_s32_cb_##n, \
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}; \
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static int wkpu_nxp_s32_init_##n(const struct device *dev) \
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{ \
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int err; \
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\
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err = wkpu_nxp_s32_init(dev); \
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if (err) { \
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return err; \
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} \
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\
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IRQ_CONNECT(DT_INST_IRQ(n, irq), DT_INST_IRQ(n, priority), \
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wkpu_nxp_s32_interrupt_handler, DEVICE_DT_INST_GET(n), \
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COND_CODE_1(CONFIG_GIC, (DT_INST_IRQ(n, flags)), (0U))); \
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irq_enable(DT_INST_IRQ(n, irq)); \
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\
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return 0; \
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} \
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DEVICE_DT_INST_DEFINE(n, wkpu_nxp_s32_init_##n, NULL, &wkpu_nxp_s32_data_##n, \
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&wkpu_nxp_s32_conf_##n, PRE_KERNEL_2, CONFIG_INTC_INIT_PRIORITY, \
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NULL);
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DT_INST_FOREACH_STATUS_OKAY(WKPU_NXP_S32_INIT_DEVICE)
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