zephyr/boards/riscv/stamp_c3
Marek Matej 6b57b3b786 soc: xtensa,riscv: esp32xx: refactor folder structure
Refactor the ESP32 target SOCs together with
all related boards. Most braking changes includes:

- changing the CONFIG_SOC_ESP32* to refer to
  the actual soc line (esp32,esp32s2,esp32s3,esp32c3)
- replacing CONFIG_SOC with the CONFIG_SOC_SERIES
- creating CONFIG_SOC_FAMILY_ESP32 to embrace all
  the ESP32 across all used architectures
- introducing CONFIG_SOC_PART_NUMBER_* to
  provide a SOC model config
- introducing the 'common' folder to hide all
  commonly used configs and files.
- updating west.yml to reflect previous changes in hal

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-07-25 18:12:33 +02:00
..
doc doc: esp32: Update the building instruction 2023-05-25 16:15:54 +02:00
support
Kconfig.board soc: xtensa,riscv: esp32xx: refactor folder structure 2023-07-25 18:12:33 +02:00
Kconfig.defconfig
Kconfig.sysbuild soc: esp32: MCUboot support 2023-05-25 16:15:54 +02:00
board.cmake
stamp_c3-pinctrl.dtsi pinctrl: esp32: fix byte garbage before banner 2023-05-11 08:26:52 -04:00
stamp_c3.dts dts: riscv: esp32c3 rework soc/sip list 2023-07-25 18:12:33 +02:00
stamp_c3.yaml boards: riscv32: Fix arch setting in board YAML 2023-04-12 09:01:48 +02:00
stamp_c3_defconfig soc: xtensa,riscv: esp32xx: refactor folder structure 2023-07-25 18:12:33 +02:00