114 lines
3.0 KiB
ArmAsm
114 lines
3.0 KiB
ArmAsm
/*
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* Copyright (c) 2016 Intel Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#define _ASMLANGUAGE
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#include <arch/nios2/asm.h>
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#include <nano_private.h>
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/* exports */
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GTEXT(__start)
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GTEXT(__reset)
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/* imports */
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GTEXT(_PrepC)
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GTEXT(_interrupt_stack)
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/* Allow use of r1/at (the assembler temporary register) in this
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* code, normally reserved for internal assembler use
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*/
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.set noat
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/*
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* Reset vector entry point into the system. Placed into special 'reset'
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* section so that the linker puts this at ALT_CPU_RESET_ADDR defined in
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* system.h
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*
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* This code can be at most 0x20 bytes, since the exception vector for Nios II
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* is usually configured to be 0x20 past the reset vector.
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*/
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SECTION_FUNC(reset, __reset)
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/* TODO initialize instruction cache, if present
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* ZEP-275
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*/
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/* Done all we need to do here, jump to __text_start */
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movhi r1, %hi(__start)
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ori r1, r1, %lo(__start)
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jmp r1
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/* Remainder of asm-land initialization code before we can jump into
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* the C domain
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*/
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SECTION_FUNC(TEXT, __start)
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/* TODO if shadow register sets enabled, ensure we are in set 0
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* ZEP-258
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*/
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/* TODO initialize data cache, if present
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* ZEP-275
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*/
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#ifdef CONFIG_INIT_STACKS
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/* Pre-populate all bytes in _interrupt_stack with 0xAA */
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movhi r1, %hi(_interrupt_stack)
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ori r1, r1, %lo(_interrupt_stack)
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movhi r2, %hi(CONFIG_ISR_STACK_SIZE)
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ori r2, r2, %lo(CONFIG_ISR_STACK_SIZE)
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subi r2, r2, 3
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/* Put constant 0xaaaaaaaa in r3 */
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movhi r3, 0xaaaa
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ori r3, r3, 0xaaaa
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1:
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/* Loop through the _interrupt_stack treating it as an array of
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* uint32_t, setting each element to r3 */
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stw r3, (r1)
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subi r2, r2, 4
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addi r1, r1, 4
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blt r0, r2, 1b
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#endif
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/* Set up the initial stack pointer to the interrupt stack, safe
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* to use this as the CPU boots up with interrupts disabled and we
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* don't turn them on until much later, when the kernel is on
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* the main stack */
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movhi sp, %hi(_interrupt_stack)
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ori sp, sp, %lo(_interrupt_stack)
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addi sp, sp, CONFIG_ISR_STACK_SIZE
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/* Create a mask in r1 which will be used to round down sp to
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* the desired alignment
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*/
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movi r1, STACK_ALIGN_SIZE
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subi r1, r1, 1
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nor r1, r1, r0
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/* Align the stack pointer */
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and sp, sp, r1
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/* TODO Setup the global pointer
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* ZEP-272
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*/
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/* TODO if shadow register sets enabled, interate through them to set
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* up. Need to clear r0, write gp, set the execption stack pointer
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* ZEP-258
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*/
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/* Jump into C domain. _PrepC zeroes BSS, copies rw data into RAM,
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* and then enters nanokernel _Cstart */
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call _PrepC
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