Ryan QIAN 5c6a3991b5 mimxrt1050: check if D-cache is enabled before enabling it. ... An issue has been confirmed in CMSIS core header file in SCB_EnableDCache when stack is in cacheable memory. Issue report: https://github.com/ARM-software/CMSIS_5/issues/331 To workaround this issue by checking if Dcache's been enabled before trying to enable it. Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>		2018-06-04 12:09:28 -05:00
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core	arm: userspace: Do not overwrite r7 during syscall.	2018-06-01 13:07:47 -04:00
include	arch: arm: Fix zero interrupt latency priority level	2018-05-31 14:58:43 -04:00
soc	mimxrt1050: check if D-cache is enabled before enabling it.	2018-06-04 12:09:28 -05:00
CMakeLists.txt	xtensa: provide XCC compiler support for Xtensa	2018-05-01 16:46:41 -04:00
Kconfig	kconfig: Make 'source' non-globbing and use 'gsource'	2018-05-08 11:14:12 +02:00
defconfig	arm: systick: Some SoCs do not have systick	2016-11-27 19:39:26 +00:00