107 lines
2.4 KiB
C
107 lines
2.4 KiB
C
/*
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* Copyright (c) 2016 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr.h>
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#include <sys_io.h>
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#include <misc/__assert.h>
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#include <power.h>
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#include <soc_power.h>
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#include <init.h>
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#include <kernel_structs.h>
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#include <soc.h>
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#include "power_states.h"
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#include "ss_power_states.h"
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#include "vreg.h"
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#if (defined(CONFIG_SYS_POWER_DEEP_SLEEP))
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extern void _power_soc_sleep(void);
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extern void _power_soc_deep_sleep(void);
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extern void _power_soc_deep_sleep_2(void);
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static void _deep_sleep(enum power_states state)
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{
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qm_power_soc_set_ss_restore_flag();
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switch (state) {
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case SYS_POWER_STATE_DEEP_SLEEP_1:
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_power_soc_sleep();
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break;
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case SYS_POWER_STATE_DEEP_SLEEP:
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_power_soc_deep_sleep();
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break;
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default:
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break;
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}
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}
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#endif
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void _sys_soc_set_power_state(enum power_states state)
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{
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switch (state) {
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case SYS_POWER_STATE_CPU_LPS:
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qm_ss_power_soc_lpss_enable();
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qm_ss_power_cpu_ss2();
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break;
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case SYS_POWER_STATE_CPU_LPS_1:
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qm_ss_power_cpu_ss2();
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break;
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case SYS_POWER_STATE_CPU_LPS_2:
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qm_ss_power_cpu_ss1(QM_SS_POWER_CPU_SS1_TIMER_ON);
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break;
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#if (defined(CONFIG_SYS_POWER_DEEP_SLEEP))
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case SYS_POWER_STATE_DEEP_SLEEP:
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case SYS_POWER_STATE_DEEP_SLEEP_1:
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_deep_sleep(state);
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break;
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case SYS_POWER_STATE_DEEP_SLEEP_2:
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qm_ss_power_soc_lpss_enable();
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qm_power_soc_set_ss_restore_flag();
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_power_soc_deep_sleep_2();
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break;
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#endif
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default:
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break;
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}
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}
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void _sys_soc_power_state_post_ops(enum power_states state)
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{
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u32_t limit;
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switch (state) {
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case SYS_POWER_STATE_CPU_LPS:
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qm_ss_power_soc_lpss_disable();
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case SYS_POWER_STATE_CPU_LPS_1:
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/* Expire the timer as it is disabled in SS2. */
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limit = _arc_v2_aux_reg_read(_ARC_V2_TMR0_LIMIT);
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_arc_v2_aux_reg_write(_ARC_V2_TMR0_COUNT, limit - 1);
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break;
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case SYS_POWER_STATE_DEEP_SLEEP:
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case SYS_POWER_STATE_DEEP_SLEEP_1:
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__builtin_arc_seti(0);
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break;
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case SYS_POWER_STATE_DEEP_SLEEP_2:
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qm_ss_power_soc_lpss_disable();
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/* If flag is cleared it means the system entered in
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* sleep state while we were in LPS. In that case, we
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* must set ARC_READY flag so x86 core can continue
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* its execution.
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*/
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if ((QM_SCSS_GP->gp0 & GP0_BIT_SLEEP_READY) == 0) {
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_quark_se_ss_ready();
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__builtin_arc_seti(0);
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} else {
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QM_SCSS_GP->gp0 &= ~GP0_BIT_SLEEP_READY;
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QM_SCSS_GP->gps0 &= ~QM_GPS0_BIT_SENSOR_WAKEUP;
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}
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break;
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default:
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break;
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}
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}
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