270 lines
10 KiB
C
270 lines
10 KiB
C
/* sensor_lsm9ds0_gyro.h - header file for LSM9DS0 gyroscope sensor driver */
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/*
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* Copyright (c) 2016 Intel Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __SENSOR_LSM9DS0_GYRO_H__
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#define __SENSOR_LSM9DS0_GYRO_H__
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#include <stdint.h>
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#include <i2c.h>
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#include <misc/util.h>
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#define DEG2RAD 0.017453292519943295769236907684
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#define LSM9DS0_GYRO_REG_WHO_AM_I_G 0x0F
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#define LSM9DS0_GYRO_VAL_WHO_AM_I_G 0xD4
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#define LSM9DS0_GYRO_REG_CTRL_REG1_G 0x20
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#define LSM9DS0_GYRO_MASK_CTRL_REG1_G_DR (BIT(7) | BIT(6))
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#define LSM9DS0_GYRO_SHIFT_CTRL_REG1_G_DR 6
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#define LSM9DS0_GYRO_MASK_CTRL_REG1_G_BW (BIT(5) | BIT(4))
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#define LSM9DS0_GYRO_SHIFT_CTRL_REG1_G_BW 4
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#define LSM9DS0_GYRO_MASK_CTRL_REG1_G_PD BIT(3)
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#define LSM9DS0_GYRO_SHIFT_CTRL_REG1_G_PD 3
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#define LSM9DS0_GYRO_MASK_CTRL_REG1_G_ZEN BIT(2)
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#define LSM9DS0_GYRO_SHIFT_CTRL_REG1_G_ZEN 2
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#define LSM9DS0_GYRO_MASK_CTRL_REG1_G_XEN BIT(1)
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#define LSM9DS0_GYRO_SHIFT_CTRL_REG1_G_XEN 1
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#define LSM9DS0_GYRO_MASK_CTRL_REG1_G_YEN BIT(0)
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#define LSM9DS0_GYRO_SHIFT_CTRL_REG1_G_YEN 0
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#define LSM9DS0_GYRO_REG_CTRL_REG2_G 0x21
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#define LSM9DS0_GYRO_MASK_CTRL_REG2_G_HPM (BIT(5) | BIT(4))
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#define LSM9DS0_GYRO_SHIFT_CTRL_REG2_G_HPM 4
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#define LSM9DS0_GYRO_MASK_CTRL_REG2_G_HPCF (BIT(3) | BIT(2) | BIT(1) | \
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BIT(0))
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#define LSM9DS0_GYRO_REG_CTRL_REG3_G 0x22
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#define LSM9DS0_GYRO_MASK_CTRL_REG3_G_I1_INT1 BIT(7)
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#define LSM9DS0_GYRO_SHIFT_CTRL_REG3_G_I1_INT1 7
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#define LSM9DS0_GYRO_MASK_CTRL_REG3_G_I1_BOOT BIT(6)
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#define LSM9DS0_GYRO_SHIFT_CTRL_REG3_G_I1_BOOT 6
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#define LSM9DS0_GYRO_MASK_CTRL_REG3_G_H_L BIT(5)
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#define LSM9DS0_GYRO_SHIFT_CTRL_REG3_G_H_L 5
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#define LSM9DS0_GYRO_MASK_CTRL_REG3_G_PP_OD BIT(4)
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#define LSM9DS0_GYRO_SHIFT_CTRL_REG3_G_PP_OD 4
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#define LSM9DS0_GYRO_MASK_CTRL_REG3_G_I2_DRDY BIT(3)
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#define LSM9DS0_GYRO_SHIFT_CTRL_REG3_G_I2_DRDY 3
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#define LSM9DS0_GYRO_MASK_CTRL_REG3_G_I2_WTM BIT(2)
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#define LSM9DS0_GYRO_SHIFT_CTRL_REG3_G_I2_WTM 2
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#define LSM9DS0_GYRO_MASK_CTRL_REG3_G_I2_OR BIT(1)
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#define LSM9DS0_GYRO_SHIFT_CTRL_REG3_G_I2_OR 1
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#define LSM9DS0_GYRO_MASK_CTRL_REG3_G_I2_E BIT(0)
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#define LSM9DS0_GYRO_SHIFT_CTRL_REG3_G_I2_E 0
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#define LSM9DS0_GYRO_REG_CTRL_REG4_G 0x23
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#define LSM9DS0_GYRO_MASK_CTRL_REG4_G_BDU BIT(7)
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#define LSM9DS0_GYRO_SHIFT_CTRL_REG4_G_BDU 7
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#define LSM9DS0_GYRO_MASK_CTRL_REG4_G_BLE BIT(6)
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#define LSM9DS0_GYRO_SHIFT_CTRL_REG4_G_BLE 6
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#define LSM9DS0_GYRO_MASK_CTRL_REG4_G_FS (BIT(5) | BIT(4))
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#define LSM9DS0_GYRO_SHIFT_CTRL_REG4_G_FS 4
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#define LSM9DS0_GYRO_MASK_CTRL_REG4_G_ST (BIT(2) | BIT(1))
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#define LSM9DS0_GYRO_SHIFT_CTRL_REG4_G_ST 1
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#define LSM9DS0_GYRO_REG_CTRL_REG5_G 0x24
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#define LSM9DS0_GYRO_MASK_CTRL_REG5_G_BOOT BIT(7)
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#define LSM9DS0_GYRO_SHIFT_CTRL_REG5_G_BOOT 7
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#define LSM9DS0_GYRO_MASK_CTRL_REG5_G_FIFO_EN BIT(6)
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#define LSM9DS0_GYRO_SHIFT_CTRL_REG5_G_FIFO_EN 6
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#define LSM9DS0_GYRO_MASK_CTRL_REG5_G_HPEN BIT(4)
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#define LSM9DS0_GYRO_SHIFT_CTRL_REG5_G_HPEN 4
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#define LSM9DS0_GYRO_MASK_CTRL_REG5_G_INT1_SEL (BIT(3) | BIT(2))
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#define LSM9DS0_GYRO_SHIFT_CTRL_REG5_G_INT1_SEL 2
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#define LSM9DS0_GYRO_MASK_CTRL_REG5_G_OUT_SEL (BIT(1) | BIT(0))
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#define LSM9DS0_GYRO_SHIFT_CTRL_REG5_G_OUT_SEL 0
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#define LSM9DS0_GYRO_REG_DATACAPTURE_G 0x25
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#define LSM9DS0_GYRO_REG_STATUS_REG_G 0x27
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#define LSM9DS0_GYRO_MASK_STATUS_REG_G_ZYXOR BIT(7)
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#define LSM9DS0_GYRO_SHIFT_STATUS_REG_G_ZYXOR 7
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#define LSM9DS0_GYRO_MASK_STATUS_REG_G_ZOR BIT(6)
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#define LSM9DS0_GYRO_SHIFT_STATUS_REG_G_ZOR 6
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#define LSM9DS0_GYRO_MASK_STATUS_REG_G_YOR BIT(5)
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#define LSM9DS0_GYRO_SHIFT_STATUS_REG_G_YOR 5
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#define LSM9DS0_GYRO_MASK_STATUS_REG_G_XOR BIT(4)
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#define LSM9DS0_GYRO_SHIFT_STATUS_REG_G_XOR 4
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#define LSM9DS0_GYRO_MASK_STATUS_REG_G_ZYXDA BIT(3)
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#define LSM9DS0_GYRO_SHIFT_STATUS_REG_G_ZYXDA 3
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#define LSM9DS0_GYRO_MASK_STATUS_REG_G_ZDA BIT(2)
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#define LSM9DS0_GYRO_SHIFT_STATUS_REG_G_ZDA 2
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#define LSM9DS0_GYRO_MASK_STATUS_REG_G_YDA BIT(1)
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#define LSM9DS0_GYRO_SHIFT_STATUS_REG_G_YDA 1
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#define LSM9DS0_GYRO_MASK_STATUS_REG_G_XDA BIT(0)
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#define LSM9DS0_GYRO_SHIFT_STATUS_REG_G_XDA 0
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#define LSM9DS0_GYRO_REG_OUT_X_L_G 0x28
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#define LSM9DS0_GYRO_REG_OUT_X_H_G 0x29
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#define LSM9DS0_GYRO_REG_OUT_Y_L_G 0x2A
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#define LSM9DS0_GYRO_REG_OUT_Y_H_G 0x2B
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#define LSM9DS0_GYRO_REG_OUT_Z_L_G 0x2C
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#define LSM9DS0_GYRO_REG_OUT_Z_H_G 0x2D
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#define LSM9DS0_GYRO_REG_FIFO_CTRL_REG_G 0x2E
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#define LSM9DS0_GYRO_MASK_FIFO_CTRL_REG_G_FM (BIT(7) | BIT(6) | BIT(5))
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#define LSM9DS0_GYRO_SHIFT_FIFO_CTRL_REG_G_FM 5
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#define LSM9DS0_GYRO_MASK_FIFO_CTRL_REG_G_WTM (BIT(4) | BIT(3) | BIT(2) | \
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BIT(1) | BIT(0))
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#define LSM9DS0_GYRO_SHIFT_FIFO_CTRL_REG_G_WTM 0
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#define LSM9DS0_GYRO_REG_FIFO_SRC_REG_G 0x2F
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#define LSM9DS0_GYRO_MASK_FIFO_SRC_REG_G_WTM BIT(7)
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#define LSM9DS0_GYRO_SHIFT_FIFO_SRC_REG_G_WTM 7
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#define LSM9DS0_GYRO_MASK_FIFO_SRC_REG_G_OVRN BIT(6)
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#define LSM9DS0_GYRO_SHIFT_FIFO_SRC_REG_G_OVRN 6
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#define LSM9DS0_GYRO_MASK_FIFO_SRC_REG_G_EMPTY BIT(5)
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#define LSM9DS0_GYRO_SHIFT_FIFO_SRC_REG_G_EMPTY 5
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#define LSM9DS0_GYRO_MASK_FIFO_SRC_REG_G_FSS (BIT(4) | BIT(3) | BIT(2) | \
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BIT(1) | BIT(0))
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#define LSM9DS0_GYRO_SHIFT_FIFO_SRC_REG_G_FSS 0
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#define LSM9DS0_GYRO_REG_INT1_CFG_G 0x30
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#define LSM9DS0_GYRO_MASK_INT1_CFG_G_ANDOR BIT(7)
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#define LSM9DS0_GYRO_SHIFT_INT1_CFG_G_ANDOR 7
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#define LSM9DS0_GYRO_MASK_INT1_CFG_G_LIR BIT(6)
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#define LSM9DS0_GYRO_SHIFT_INT1_CFG_G_LIR 6
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#define LSM9DS0_GYRO_MASK_INT1_CFG_G_ZHIE BIT(5)
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#define LSM9DS0_GYRO_SHIFT_INT1_CFG_G_ZHIE 5
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#define LSM9DS0_GYRO_MASK_INT1_CFG_G_ZLIE BIT(4)
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#define LSM9DS0_GYRO_SHIFT_INT1_CFG_G_ZLIE 4
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#define LSM9DS0_GYRO_MASK_INT1_CFG_G_YHIE BIT(3)
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#define LSM9DS0_GYRO_SHIFT_INT1_CFG_G_YHIE 3
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#define LSM9DS0_GYRO_MASK_INT1_CFG_G_YLIE BIT(2)
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#define LSM9DS0_GYRO_SHIFT_INT1_CFG_G_YLIE 2
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#define LSM9DS0_GYRO_MASK_INT1_CFG_G_XHIE BIT(1)
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#define LSM9DS0_GYRO_SHIFT_INT1_CFG_G_XHIE 1
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#define LSM9DS0_GYRO_MASK_INT1_CFG_G_XLIE BIT(0)
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#define LSM9DS0_GYRO_SHIFT_INT1_CFG_G_XLIE 0
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#define LSM9DS0_GYRO_REG_INT1_SRC_G 0x31
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#define LSM9DS0_GYRO_MASK_INT1_SRC_G_IA BIT(6)
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#define LSM9DS0_GYRO_SHIFT_INT1_SRC_G_IA 6
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#define LSM9DS0_GYRO_MASK_INT1_SRC_G_ZH BIT(5)
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#define LSM9DS0_GYRO_SHIFT_INT1_SRC_G_ZH 5
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#define LSM9DS0_GYRO_MASK_INT1_SRC_G_ZL BIT(4)
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#define LSM9DS0_GYRO_SHIFT_INT1_SRC_G_ZL 4
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#define LSM9DS0_GYRO_MASK_INT1_SRC_G_YH BIT(3)
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#define LSM9DS0_GYRO_SHIFT_INT1_SRC_G_YH 3
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#define LSM9DS0_GYRO_MASK_INT1_SRC_G_YL BIT(2)
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#define LSM9DS0_GYRO_SHIFT_INT1_SRC_G_YL 2
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#define LSM9DS0_GYRO_MASK_INT1_SRC_G_XH BIT(1)
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#define LSM9DS0_GYRO_SHIFT_INT1_SRC_G_XH 1
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#define LSM9DS0_GYRO_MASK_INT1_SRC_G_XL BIT(0)
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#define LSM9DS0_GYRO_SHIFT_INT1_SRC_G_XL 0
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#define LSM9DS0_GYRO_REG_INT1_THS_XH_G 0x32
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#define LSM9DS0_GYRO_MASK_INT1_THS_XH_G (BIT(6) | BIT(5) | BIT(4) | \
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BIT(3) | BIT(2) | BIT(1) | \
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BIT(0))
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#define LSM9DS0_GYRO_REG_INT1_THS_XL_G 0x33
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#define LSM9DS0_GYRO_REG_INT1_THS_YH_G 0x34
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#define LSM9DS0_GYRO_MASK_INT1_THS_YH_G (BIT(6) | BIT(5) | BIT(4) | \
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BIT(3) | BIT(2) | BIT(1) | \
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BIT(0))
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#define LSM9DS0_GYRO_REG_INT1_THS_YL_G 0x35
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#define LSM9DS0_GYRO_REG_INT1_THS_ZH_G 0x36
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#define LSM9DS0_GYRO_MASK_INT1_THS_ZH_G (BIT(6) | BIT(5) | BIT(4) | \
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BIT(3) | BIT(2) | BIT(1) | \
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BIT(0))
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#define LSM9DS0_GYRO_REG_INT1_THS_ZL_G 0x37
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#define LSM9DS0_GYRO_REG_INT1_DURATION_G 0x38
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#define LSM9DS0_GYRO_MASK_INT1_DURATION_G_WAIT BIT(7)
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#define LSM9DS0_GYRO_SHIFT_INT1_DURATION_G_WAIT 7
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#define LSM9DS0_GYRO_MASK_INT1_DURATION_G_D (BIT(6) | BIT(5) | BIT(4) | \
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BIT(3) | BIT(2) | BIT(1) | \
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BIT(0))
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#define LSM9DS0_GYRO_SHIFT_INT1_DURATION_G_D 0
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#define LSM9DS0_GYRO_I2C_ADDR CONFIG_LSM9DS0_GYRO_I2C_ADDR
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#if defined(CONFIG_LSM9DS0_GYRO_FULLSCALE_245)
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#define LSM9DS0_GYRO_DEFAULT_FULLSCALE 0
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#elif defined(CONFIG_LSM9DS0_GYRO_FULLSCALE_500)
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#define LSM9DS0_GYRO_DEFAULT_FULLSCALE 1
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#elif defined(CONFIG_LSM9DS0_GYRO_FULLSCALE_2000)
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#define LSM9DS0_GYRO_DEFAULT_FULLSCALE 2
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#endif
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#if defined(CONFIG_LSM9DS0_GYRO_SAMPLING_RATE_95)
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#define LSM9DS0_GYRO_DEFAULT_SAMPLING_RATE 0
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#elif defined(CONFIG_LSM9DS0_GYRO_SAMPLING_RATE_190)
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#define LSM9DS0_GYRO_DEFAULT_SAMPLING_RATE 1
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#elif defined(CONFIG_LSM9DS0_GYRO_SAMPLING_RATE_380)
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#define LSM9DS0_GYRO_DEFAULT_SAMPLING_RATE 2
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#elif defined(CONFIG_LSM9DS0_GYRO_SAMPLING_RATE_760)
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#define LSM9DS0_GYRO_DEFAULT_SAMPLING_RATE 3
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#endif
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#if defined(CONFIG_LSM9DS0_GYRO_SAMPLING_RATE_RUNTIME) || \
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defined(CONFIG_LSM9DS0_GYRO_FULLSCALE_RUNTIME)
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#define LSM9DS0_GYRO_SET_ATTR
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#endif
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struct lsm9ds0_gyro_config {
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char *i2c_master_dev_name;
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uint16_t i2c_slave_addr;
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#if CONFIG_LSM9DS0_GYRO_TRIGGER_DRDY
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char *gpio_drdy_dev_name;
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uint8_t gpio_drdy_int_pin;
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#endif
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};
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struct lsm9ds0_gyro_data {
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struct device *i2c_master;
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#if defined(CONFIG_LSM9DS0_GYRO_TRIGGERS)
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struct nano_sem sem;
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#endif
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#if defined(CONFIG_LSM9DS0_GYRO_TRIGGER_DRDY)
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char __stack fiber_stack[CONFIG_LSM9DS0_GYRO_FIBER_STACK_SIZE];
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struct device *dev;
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struct device *gpio_drdy;
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struct gpio_callback gpio_cb;
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struct sensor_trigger trigger_drdy;
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sensor_trigger_handler_t handler_drdy;
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#endif
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int sample_x, sample_y, sample_z;
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#if defined(CONFIG_LSM9DS0_GYRO_FULLSCALE_RUNTIME)
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uint8_t sample_fs;
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uint8_t fs;
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#endif
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};
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#if defined(CONFIG_LSM9DS0_GYRO_TRIGGER_DRDY)
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int lsm9ds0_gyro_trigger_set(struct device *dev,
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const struct sensor_trigger *trig,
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sensor_trigger_handler_t handler);
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int lsm9ds0_gyro_init_interrupt(struct device *dev);
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#endif
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#define SYS_LOG_DOMAIN "LSM9DS0_GYRO"
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#define SYS_LOG_LEVEL CONFIG_LSM9DS0_GYRO_SYS_LOG_LEVEL
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#include <misc/sys_log.h>
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#endif /* __SENSOR_LSM9DS0_GYRO_H__ */
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