150 lines
3.5 KiB
C
150 lines
3.5 KiB
C
/*
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* Copyright (c) 2018 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <drivers/system_timer.h>
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#include <sys_clock.h>
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#include <spinlock.h>
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#include <arch/arm/cortex_m/cmsis.h>
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void _ExcExit(void);
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/* Minimum cycles in the future to try to program. */
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#define MIN_DELAY 512
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#define COUNTER_MAX 0x00ffffff
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#define TIMER_STOPPED 0xff000000
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#define CYC_PER_TICK (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC \
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/ CONFIG_SYS_CLOCK_TICKS_PER_SEC)
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#define MAX_TICKS ((COUNTER_MAX / CYC_PER_TICK) - 1)
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#define MAX_CYCLES (MAX_TICKS * CYC_PER_TICK)
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#define TICKLESS (IS_ENABLED(CONFIG_TICKLESS_KERNEL) && \
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!IS_ENABLED(CONFIG_QEMU_TICKLESS_WORKAROUND))
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static struct k_spinlock lock;
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static u32_t last_load;
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static u32_t cycle_count;
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static u32_t announced_cycles;
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static volatile u32_t ctrl_cache; /* overflow bit clears on read! */
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static u32_t elapsed(void)
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{
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u32_t val, ov;
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do {
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val = SysTick->VAL & COUNTER_MAX;
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ctrl_cache |= SysTick->CTRL;
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} while (SysTick->VAL > val);
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ov = (ctrl_cache & SysTick_CTRL_COUNTFLAG_Msk) ? last_load : 0;
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return (last_load - val) + ov;
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}
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/* Callout out of platform assembly, not hooked via IRQ_CONNECT... */
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void _timer_int_handler(void *arg)
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{
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ARG_UNUSED(arg);
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u32_t dticks;
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cycle_count += last_load;
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dticks = (cycle_count - announced_cycles) / CYC_PER_TICK;
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announced_cycles += dticks * CYC_PER_TICK;
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ctrl_cache = SysTick->CTRL; /* Reset overflow flag */
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ctrl_cache = 0U;
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z_clock_announce(TICKLESS ? dticks : 1);
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_ExcExit();
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}
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int z_clock_driver_init(struct device *device)
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{
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NVIC_SetPriority(SysTick_IRQn, _IRQ_PRIO_OFFSET);
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last_load = CYC_PER_TICK;
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SysTick->LOAD = last_load;
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SysTick->VAL = 0; /* resets timer to last_load */
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SysTick->CTRL |= (SysTick_CTRL_ENABLE_Msk |
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SysTick_CTRL_TICKINT_Msk |
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SysTick_CTRL_CLKSOURCE_Msk);
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return 0;
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}
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void z_clock_set_timeout(s32_t ticks, bool idle)
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{
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/* Fast CPUs and a 24 bit counter mean that even idle systems
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* need to wake up multiple times per second. If the kernel
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* allows us to miss tick announcements in idle, then shut off
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* the counter. (Note: we can assume if idle==true that
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* interrupts are already disabled)
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*/
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if (IS_ENABLED(CONFIG_TICKLESS_IDLE) && idle && ticks == K_FOREVER) {
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SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
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last_load = TIMER_STOPPED;
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return;
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}
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#if defined(CONFIG_TICKLESS_KERNEL) && !defined(CONFIG_QEMU_TICKLESS_WORKAROUND)
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u32_t delay;
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ticks = min(MAX_TICKS, max(ticks - 1, 0));
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/* Desired delay in the future */
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delay = (ticks == 0) ? MIN_DELAY : ticks * CYC_PER_TICK;
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k_spinlock_key_t key = k_spin_lock(&lock);
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cycle_count += elapsed();
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/* Round delay up to next tick boundary */
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delay = delay + (cycle_count - announced_cycles);
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delay = ((delay + CYC_PER_TICK - 1) / CYC_PER_TICK) * CYC_PER_TICK;
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last_load = delay - (cycle_count - announced_cycles);
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SysTick->LOAD = last_load;
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SysTick->VAL = 0; /* resets timer to last_load */
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k_spin_unlock(&lock, key);
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#endif
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}
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u32_t z_clock_elapsed(void)
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{
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if (!TICKLESS) {
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return 0;
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}
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k_spinlock_key_t key = k_spin_lock(&lock);
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u32_t cyc = elapsed() + cycle_count - announced_cycles;
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k_spin_unlock(&lock, key);
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return cyc / CYC_PER_TICK;
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}
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u32_t _timer_cycle_get_32(void)
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{
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k_spinlock_key_t key = k_spin_lock(&lock);
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u32_t ret = elapsed() + cycle_count;
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k_spin_unlock(&lock, key);
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return ret;
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}
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void z_clock_idle_exit(void)
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{
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if (last_load == TIMER_STOPPED) {
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SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
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}
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}
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void sys_clock_disable(void)
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{
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SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
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}
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