18 lines
433 B
C
18 lines
433 B
C
/*
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* Copyright (c) 2019 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* SoC level DTS fixup file */
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#if defined(CONFIG_SOC_OPENISA_RV32M1_RISCV32)
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#define DT_FLASH_DEV_BASE_ADDRESS DT_OPENISA_RV32M1_FTFE_40023000_BASE_ADDRESS
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#define DT_FLASH_DEV_NAME DT_OPENISA_RV32M1_FTFE_40023000_LABEL
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#define DT_START_UP_ENTRY_OFFSET 0x80
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#endif /* CONFIG_SOC_OPENISA_RV32M1_RISCV32 */
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/* End of SoC Level DTS fixup file */
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