Mateusz Holenko ebd349091a dts: riscv32: fix reg-names for liteeth ... Liteeth exposes two memory regions: * set of rx/tx buffers (aka slots) to exchange packets, * control and status registers. Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>		2019-07-23 10:51:21 +02:00
..
arc	dts: Add information about system bus frequency to the dts	2019-07-17 21:53:36 +02:00
arm	dts: add label property to all jedec,spi-nor nodes	2019-07-20 17:23:08 -04:00
bindings	dts/bindings: Make pwm-leds label optional	2019-07-23 04:09:19 -04:00
common	dts: flash simulator cleanup	2019-04-26 04:04:19 -07:00
nios2	dts: nios2: fix flash node name	2019-07-02 18:38:23 -04:00
posix	dts: posix: Add DTS support for POSIX architecture	2019-05-28 21:14:19 -04:00
riscv32	dts: riscv32: fix reg-names for liteeth	2019-07-23 10:51:21 +02:00
x86	dts: Remove unused virtualcom device node from dts	2019-07-18 11:24:40 +02:00
xtensa	dts: Add information about system bus frequency to the dts	2019-07-17 21:53:36 +02:00
Kconfig	license: cleanup: add SPDX Apache-2.0 license identifier	2019-04-07 08:45:22 -04:00