141 lines
2.8 KiB
Plaintext
141 lines
2.8 KiB
Plaintext
/*
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* Copyright (c) 2022 Teslabs Engineering S.L.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/gd/gd32e50x/gd32e50x.dtsi>
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/ {
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soc {
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timer7: timer@40013400 {
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compatible = "gd,gd32-timer";
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reg = <0x40013400 0x400>;
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interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
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interrupt-names = "brk", "up", "trgcom", "cc";
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clocks = <&cctl GD32_CLOCK_TIMER7>;
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resets = <&rctl GD32_RESET_TIMER7>;
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is-advanced;
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channels = <4>;
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status = "disabled";
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pwm {
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compatible = "gd,gd32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timer8: timer@40014c00 {
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compatible = "gd,gd32-timer";
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reg = <0x40014c00 0x400>;
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interrupts = <24 0>;
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interrupt-names = "global";
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clocks = <&cctl GD32_CLOCK_TIMER8>;
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resets = <&rctl GD32_RESET_TIMER8>;
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channels = <2>;
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status = "disabled";
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pwm {
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compatible = "gd,gd32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timer9: timer@40015000 {
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compatible = "gd,gd32-timer";
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reg = <0x40015000 0x400>;
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interrupts = <25 0>;
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interrupt-names = "global";
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clocks = <&cctl GD32_CLOCK_TIMER9>;
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resets = <&rctl GD32_RESET_TIMER9>;
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channels = <1>;
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status = "disabled";
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pwm {
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compatible = "gd,gd32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timer10: timer@40015400 {
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compatible = "gd,gd32-timer";
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reg = <0x40015400 0x400>;
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interrupts = <26 0>;
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interrupt-names = "global";
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clocks = <&cctl GD32_CLOCK_TIMER10>;
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resets = <&rctl GD32_RESET_TIMER10>;
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channels = <1>;
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status = "disabled";
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pwm {
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compatible = "gd,gd32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timer11: timer@40001800 {
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compatible = "gd,gd32-timer";
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reg = <0x40001800 0x400>;
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interrupts = <43 0>;
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interrupt-names = "global";
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clocks = <&cctl GD32_CLOCK_TIMER11>;
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resets = <&rctl GD32_RESET_TIMER11>;
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channels = <2>;
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status = "disabled";
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pwm {
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compatible = "gd,gd32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timer12: timer@40001c00 {
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compatible = "gd,gd32-timer";
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reg = <0x40001c00 0x400>;
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interrupts = <44 0>;
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interrupt-names = "global";
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clocks = <&cctl GD32_CLOCK_TIMER12>;
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resets = <&rctl GD32_RESET_TIMER12>;
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channels = <1>;
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status = "disabled";
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pwm {
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compatible = "gd,gd32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timer13: timer@40002000 {
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compatible = "gd,gd32-timer";
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reg = <0x40002000 0x400>;
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interrupts = <45 0>;
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interrupt-names = "global";
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clocks = <&cctl GD32_CLOCK_TIMER13>;
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resets = <&rctl GD32_RESET_TIMER13>;
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channels = <1>;
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status = "disabled";
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pwm {
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compatible = "gd,gd32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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};
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};
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&flash0 {
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reg = <0x08000000 DT_SIZE_K(512)>;
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};
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&sram0 {
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reg = <0x20000000 DT_SIZE_K(128)>;
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};
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