113 lines
2.5 KiB
C
113 lines
2.5 KiB
C
/*
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* Copyright (c) 2016 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr.h>
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#include <sys_io.h>
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#include <misc/__assert.h>
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#include <power.h>
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#include <soc_power.h>
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#include <soc.h>
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#include "power_states.h"
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#define _REG_TIMER_ICR ((volatile u32_t *) \
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(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_TIMER_ICR))
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/* Variables used to save CPU state */
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u64_t _pm_save_gdtr;
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u64_t _pm_save_idtr;
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u32_t _pm_save_esp;
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extern void _power_soc_sleep(void);
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extern void _power_restore_cpu_context(void);
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extern void _power_soc_deep_sleep(void);
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#if (defined(CONFIG_SYS_POWER_DEEP_SLEEP))
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static u32_t *__x86_restore_info =
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(u32_t *)CONFIG_BSP_SHARED_RESTORE_INFO_RAM_ADDR;
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static void _deep_sleep(enum power_states state)
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{
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/*
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* Setting resume vector inside the restore_cpu_context
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* function since we have nothing to do before cpu context
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* is restored. If necessary, it is possible to set the
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* resume vector to a location where additional processing
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* can be done before cpu context is restored and control
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* transferred to _sys_soc_suspend.
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*/
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qm_x86_set_resume_vector(_power_restore_cpu_context,
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*__x86_restore_info);
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qm_power_soc_set_x86_restore_flag();
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switch (state) {
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case SYS_POWER_STATE_DEEP_SLEEP_1:
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_power_soc_sleep();
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break;
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case SYS_POWER_STATE_DEEP_SLEEP:
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case SYS_POWER_STATE_DEEP_SLEEP_2:
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_power_soc_deep_sleep();
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break;
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default:
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break;
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}
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}
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#endif
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void _sys_soc_set_power_state(enum power_states state)
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{
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switch (state) {
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case SYS_POWER_STATE_CPU_LPS:
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qm_power_cpu_c2lp();
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break;
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case SYS_POWER_STATE_CPU_LPS_1:
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qm_power_cpu_c2();
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break;
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case SYS_POWER_STATE_CPU_LPS_2:
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qm_power_cpu_c1();
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break;
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#if (defined(CONFIG_SYS_POWER_DEEP_SLEEP))
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case SYS_POWER_STATE_DEEP_SLEEP:
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case SYS_POWER_STATE_DEEP_SLEEP_1:
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case SYS_POWER_STATE_DEEP_SLEEP_2:
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_deep_sleep(state);
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break;
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#endif
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default:
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break;
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}
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}
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void _sys_soc_power_state_post_ops(enum power_states state)
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{
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switch (state) {
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case SYS_POWER_STATE_CPU_LPS:
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*_REG_TIMER_ICR = 1;
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case SYS_POWER_STATE_CPU_LPS_1:
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__asm__ volatile("sti");
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break;
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#if (defined(CONFIG_SYS_POWER_DEEP_SLEEP))
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case SYS_POWER_STATE_DEEP_SLEEP_2:
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#ifdef CONFIG_ARC_INIT
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_arc_init(NULL);
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#endif /* CONFIG_ARC_INIT */
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/* Fallthrough */
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case SYS_POWER_STATE_DEEP_SLEEP:
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case SYS_POWER_STATE_DEEP_SLEEP_1:
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__asm__ volatile("sti");
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break;
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#endif
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default:
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break;
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}
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}
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bool _sys_soc_power_state_is_arc_ready(void)
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{
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return QM_SCSS_GP->gp0 & GP0_BIT_SLEEP_READY ? true : false;
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}
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