556 lines
14 KiB
C
556 lines
14 KiB
C
/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_imx_flexspi_mx25um51345g
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#include <drivers/flash.h>
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#include <logging/log.h>
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#include <sys/util.h>
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#include "spi_nor.h"
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#include "memc_mcux_flexspi.h"
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#ifdef CONFIG_HAS_MCUX_CACHE
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#include <fsl_cache.h>
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#endif
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#define NOR_WRITE_SIZE 1
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#define NOR_ERASE_VALUE 0xff
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#ifdef CONFIG_FLASH_MCUX_FLEXSPI_NOR_WRITE_BUFFER
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static uint8_t nor_write_buf[SPI_NOR_PAGE_SIZE];
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#endif
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LOG_MODULE_REGISTER(flash_flexspi_nor, CONFIG_FLASH_LOG_LEVEL);
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enum {
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/* Instructions matching with XIP layout */
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READ,
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WRITE_ENABLE_OPI,
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WRITE_ENABLE,
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ERASE_SECTOR,
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PAGE_PROGRAM_INPUT,
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PAGE_PROGRAM,
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READ_ID_OPI,
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ENTER_OPI,
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READ_STATUS_REG,
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ERASE_CHIP,
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};
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struct flash_flexspi_nor_config {
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char *controller_label;
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flexspi_port_t port;
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flexspi_device_config_t config;
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struct flash_pages_layout layout;
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struct flash_parameters flash_parameters;
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};
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struct flash_flexspi_nor_data {
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const struct device *controller;
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};
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static const uint32_t flash_flexspi_nor_lut[][4] = {
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[READ_ID_OPI] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x9F,
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kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x60),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20,
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kFLEXSPI_Command_DUMMY_DDR, kFLEXSPI_8PAD, 0x16),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
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},
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[READ_STATUS_REG] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x05,
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kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xFA),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_8PAD, 0x20,
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kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_8PAD, 0x14),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_8PAD, 0x04,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
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},
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[WRITE_ENABLE] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
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},
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[WRITE_ENABLE_OPI] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x06,
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kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xF9),
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},
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[ERASE_SECTOR] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x21,
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kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xDE),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_8PAD, 0x20,
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kFLEXSPI_Command_STOP, kFLEXSPI_8PAD, 0),
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},
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[ERASE_CHIP] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x60,
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kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x9F),
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},
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[READ] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xEC,
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kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x13),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_8PAD, 0x20,
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kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_8PAD, 0x14),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_8PAD, 0x04,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
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},
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[PAGE_PROGRAM] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x12,
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kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xED),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_8PAD, 0x20,
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kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_8PAD, 0x04),
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},
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[ENTER_OPI] = {
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x72,
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kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x20),
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04,
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kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
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},
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};
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static int flash_flexspi_nor_get_vendor_id(const struct device *dev,
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uint8_t *vendor_id)
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{
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const struct flash_flexspi_nor_config *config = dev->config;
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struct flash_flexspi_nor_data *data = dev->data;
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uint32_t buffer = 0;
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int ret;
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flexspi_transfer_t transfer = {
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.deviceAddress = 0,
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.port = config->port,
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.cmdType = kFLEXSPI_Read,
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.SeqNumber = 1,
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.seqIndex = READ_ID_OPI,
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.data = &buffer,
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.dataSize = 1,
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};
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LOG_DBG("Reading id");
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ret = memc_flexspi_transfer(data->controller, &transfer);
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*vendor_id = buffer;
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return ret;
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}
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static int flash_flexspi_nor_read_status(const struct device *dev,
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uint32_t *status)
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{
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const struct flash_flexspi_nor_config *config = dev->config;
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struct flash_flexspi_nor_data *data = dev->data;
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flexspi_transfer_t transfer = {
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.deviceAddress = 0,
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.port = config->port,
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.cmdType = kFLEXSPI_Read,
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.SeqNumber = 1,
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.seqIndex = READ_STATUS_REG,
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.data = status,
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.dataSize = 1,
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};
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LOG_DBG("Reading status register");
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return memc_flexspi_transfer(data->controller, &transfer);
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}
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static int flash_flexspi_nor_write_status(const struct device *dev,
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uint32_t *status)
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{
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const struct flash_flexspi_nor_config *config = dev->config;
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struct flash_flexspi_nor_data *data = dev->data;
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flexspi_transfer_t transfer = {
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.deviceAddress = 0,
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.port = config->port,
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.cmdType = kFLEXSPI_Write,
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.SeqNumber = 1,
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.seqIndex = ENTER_OPI,
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.data = status,
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.dataSize = 1,
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};
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LOG_DBG("Writing status register");
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return memc_flexspi_transfer(data->controller, &transfer);
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}
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static int flash_flexspi_nor_write_enable(const struct device *dev,
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bool enableOctal)
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{
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const struct flash_flexspi_nor_config *config = dev->config;
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struct flash_flexspi_nor_data *data = dev->data;
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flexspi_transfer_t transfer;
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transfer.deviceAddress = 0;
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transfer.port = config->port;
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transfer.cmdType = kFLEXSPI_Command;
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transfer.SeqNumber = 1;
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if (enableOctal) {
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transfer.seqIndex = WRITE_ENABLE_OPI;
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} else {
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transfer.seqIndex = WRITE_ENABLE;
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}
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transfer.data = NULL;
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transfer.dataSize = 0;
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LOG_DBG("Enabling write");
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return memc_flexspi_transfer(data->controller, &transfer);
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}
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static int flash_flexspi_nor_erase_sector(const struct device *dev,
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off_t offset)
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{
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const struct flash_flexspi_nor_config *config = dev->config;
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struct flash_flexspi_nor_data *data = dev->data;
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flexspi_transfer_t transfer = {
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.deviceAddress = offset,
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.port = config->port,
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.cmdType = kFLEXSPI_Command,
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.SeqNumber = 1,
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.seqIndex = ERASE_SECTOR,
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.data = NULL,
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.dataSize = 0,
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};
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LOG_DBG("Erasing sector at 0x%08x", offset);
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return memc_flexspi_transfer(data->controller, &transfer);
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}
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static int flash_flexspi_nor_erase_chip(const struct device *dev)
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{
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const struct flash_flexspi_nor_config *config = dev->config;
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struct flash_flexspi_nor_data *data = dev->data;
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flexspi_transfer_t transfer = {
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.deviceAddress = 0,
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.port = config->port,
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.cmdType = kFLEXSPI_Command,
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.SeqNumber = 1,
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.seqIndex = ERASE_CHIP,
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.data = NULL,
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.dataSize = 0,
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};
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LOG_DBG("Erasing chip");
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return memc_flexspi_transfer(data->controller, &transfer);
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}
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static int flash_flexspi_nor_page_program(const struct device *dev,
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off_t offset, const void *buffer, size_t len)
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{
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const struct flash_flexspi_nor_config *config = dev->config;
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struct flash_flexspi_nor_data *data = dev->data;
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flexspi_transfer_t transfer = {
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.deviceAddress = offset,
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.port = config->port,
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.cmdType = kFLEXSPI_Write,
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.SeqNumber = 1,
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.seqIndex = PAGE_PROGRAM,
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.data = (uint32_t *) buffer,
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.dataSize = len,
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};
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LOG_DBG("Page programming %d bytes to 0x%08x", len, offset);
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return memc_flexspi_transfer(data->controller, &transfer);
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}
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static int flash_flexspi_nor_wait_bus_busy(const struct device *dev)
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{
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uint32_t status = 0;
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int ret;
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do {
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ret = flash_flexspi_nor_read_status(dev, &status);
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LOG_DBG("status: 0x%x", status);
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if (ret) {
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LOG_ERR("Could not read status");
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return ret;
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}
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} while (status & BIT(0));
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return 0;
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}
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static int flash_flexspi_enable_octal_mode(const struct device *dev)
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{
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struct flash_flexspi_nor_data *data = dev->data;
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/* FLASH_ENABLE_OCTAL_CMD: (01 = STR OPI Enable) */
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uint32_t status = 0x01;
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flash_flexspi_nor_write_enable(dev, false);
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flash_flexspi_nor_write_status(dev, &status);
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flash_flexspi_nor_wait_bus_busy(dev);
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memc_flexspi_reset(data->controller);
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return 0;
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}
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static int flash_flexspi_nor_read(const struct device *dev, off_t offset,
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void *buffer, size_t len)
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{
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const struct flash_flexspi_nor_config *config = dev->config;
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struct flash_flexspi_nor_data *data = dev->data;
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uint8_t *src = memc_flexspi_get_ahb_address(data->controller,
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config->port,
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offset);
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memcpy(buffer, src, len);
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return 0;
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}
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static int flash_flexspi_nor_write(const struct device *dev, off_t offset,
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const void *buffer, size_t len)
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{
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const struct flash_flexspi_nor_config *config = dev->config;
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struct flash_flexspi_nor_data *data = dev->data;
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size_t size = len;
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uint8_t *src = (uint8_t *) buffer;
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int i;
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unsigned int key = 0;
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uint8_t *dst = memc_flexspi_get_ahb_address(data->controller,
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config->port,
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offset);
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if (memc_flexspi_is_running_xip(data->controller)) {
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key = irq_lock();
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}
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while (len) {
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/* If the offset isn't a multiple of the NOR page size, we first need
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* to write the remaining part that fits, otherwise the write could
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* be wrapped around within the same page
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*/
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i = MIN(SPI_NOR_PAGE_SIZE - (offset % SPI_NOR_PAGE_SIZE), len);
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#ifdef CONFIG_FLASH_MCUX_FLEXSPI_NOR_WRITE_BUFFER
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memcpy(nor_write_buf, src, i);
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#endif
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flash_flexspi_nor_write_enable(dev, true);
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#ifdef CONFIG_FLASH_MCUX_FLEXSPI_NOR_WRITE_BUFFER
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flash_flexspi_nor_page_program(dev, offset, nor_write_buf, i);
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#else
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flash_flexspi_nor_page_program(dev, offset, src, i);
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#endif
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flash_flexspi_nor_wait_bus_busy(dev);
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memc_flexspi_reset(data->controller);
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src += i;
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offset += i;
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len -= i;
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}
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if (memc_flexspi_is_running_xip(data->controller)) {
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irq_unlock(key);
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}
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#ifdef CONFIG_HAS_MCUX_CACHE
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DCACHE_InvalidateByRange((uint32_t) dst, size);
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#endif
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return 0;
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}
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static int flash_flexspi_nor_erase(const struct device *dev, off_t offset,
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size_t size)
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{
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const struct flash_flexspi_nor_config *config = dev->config;
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struct flash_flexspi_nor_data *data = dev->data;
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int num_sectors = size / SPI_NOR_SECTOR_SIZE;
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int i;
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unsigned int key = 0;
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uint8_t *dst = memc_flexspi_get_ahb_address(data->controller,
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config->port,
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offset);
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if (offset % SPI_NOR_SECTOR_SIZE) {
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LOG_ERR("Invalid offset");
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return -EINVAL;
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}
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if (size % SPI_NOR_SECTOR_SIZE) {
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LOG_ERR("Invalid size");
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return -EINVAL;
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}
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if (memc_flexspi_is_running_xip(data->controller)) {
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key = irq_lock();
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}
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if ((offset == 0) && (size == config->config.flashSize * KB(1))) {
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flash_flexspi_nor_write_enable(dev, true);
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flash_flexspi_nor_erase_chip(dev);
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flash_flexspi_nor_wait_bus_busy(dev);
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memc_flexspi_reset(data->controller);
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} else {
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for (i = 0; i < num_sectors; i++) {
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flash_flexspi_nor_write_enable(dev, true);
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flash_flexspi_nor_erase_sector(dev, offset);
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flash_flexspi_nor_wait_bus_busy(dev);
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memc_flexspi_reset(data->controller);
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offset += SPI_NOR_SECTOR_SIZE;
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}
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}
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if (memc_flexspi_is_running_xip(data->controller)) {
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irq_unlock(key);
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}
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#ifdef CONFIG_HAS_MCUX_CACHE
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DCACHE_InvalidateByRange((uint32_t) dst, size);
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#endif
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return 0;
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}
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static const struct flash_parameters *flash_flexspi_nor_get_parameters(
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const struct device *dev)
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{
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const struct flash_flexspi_nor_config *config = dev->config;
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return &config->flash_parameters;
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}
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#if defined(CONFIG_FLASH_PAGE_LAYOUT)
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static void flash_flexspi_nor_pages_layout(const struct device *dev,
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const struct flash_pages_layout **layout, size_t *layout_size)
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{
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const struct flash_flexspi_nor_config *config = dev->config;
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*layout = &config->layout;
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*layout_size = 1;
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}
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#endif /* CONFIG_FLASH_PAGE_LAYOUT */
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static int flash_flexspi_nor_init(const struct device *dev)
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{
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const struct flash_flexspi_nor_config *config = dev->config;
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struct flash_flexspi_nor_data *data = dev->data;
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uint8_t vendor_id;
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data->controller = device_get_binding(config->controller_label);
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if (data->controller == NULL) {
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LOG_ERR("Could not find controller");
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return -EINVAL;
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}
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if (!memc_flexspi_is_running_xip(data->controller) &&
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memc_flexspi_set_device_config(data->controller, &config->config,
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config->port)) {
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LOG_ERR("Could not set device configuration");
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return -EINVAL;
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}
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if (memc_flexspi_update_lut(data->controller, 0,
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(const uint32_t *) flash_flexspi_nor_lut,
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sizeof(flash_flexspi_nor_lut) / 4)) {
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LOG_ERR("Could not update lut");
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return -EINVAL;
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}
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memc_flexspi_reset(data->controller);
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if (flash_flexspi_enable_octal_mode(dev)) {
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LOG_ERR("Could not enable octal mode");
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return -EIO;
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}
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if (flash_flexspi_nor_get_vendor_id(dev, &vendor_id)) {
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LOG_ERR("Could not read vendor id");
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return -EIO;
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}
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LOG_DBG("Vendor id: 0x%0x", vendor_id);
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return 0;
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}
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static const struct flash_driver_api flash_flexspi_nor_api = {
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.erase = flash_flexspi_nor_erase,
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.write = flash_flexspi_nor_write,
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.read = flash_flexspi_nor_read,
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.get_parameters = flash_flexspi_nor_get_parameters,
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#if defined(CONFIG_FLASH_PAGE_LAYOUT)
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.page_layout = flash_flexspi_nor_pages_layout,
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#endif
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};
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#define CONCAT3(x, y, z) x ## y ## z
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#define CS_INTERVAL_UNIT(unit) \
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CONCAT3(kFLEXSPI_CsIntervalUnit, unit, SckCycle)
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#define AHB_WRITE_WAIT_UNIT(unit) \
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CONCAT3(kFLEXSPI_AhbWriteWaitUnit, unit, AhbCycle)
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#define FLASH_FLEXSPI_DEVICE_CONFIG(n) \
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{ \
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.flexspiRootClk = MHZ(120), \
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.flashSize = DT_INST_PROP(n, size) / 8 / KB(1), \
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.CSIntervalUnit = \
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CS_INTERVAL_UNIT( \
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DT_INST_PROP(n, cs_interval_unit)), \
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.CSInterval = DT_INST_PROP(n, cs_interval), \
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.CSHoldTime = DT_INST_PROP(n, cs_hold_time), \
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.CSSetupTime = DT_INST_PROP(n, cs_setup_time), \
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.dataValidTime = DT_INST_PROP(n, data_valid_time), \
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.columnspace = DT_INST_PROP(n, column_space), \
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.enableWordAddress = DT_INST_PROP(n, word_addressable), \
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.AWRSeqIndex = 0, \
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.AWRSeqNumber = 0, \
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.ARDSeqIndex = READ, \
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.ARDSeqNumber = 1, \
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.AHBWriteWaitUnit = \
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AHB_WRITE_WAIT_UNIT( \
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DT_INST_PROP(n, ahb_write_wait_unit)), \
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.AHBWriteWaitInterval = \
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DT_INST_PROP(n, ahb_write_wait_interval), \
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} \
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#define FLASH_FLEXSPI_NOR(n) \
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static const struct flash_flexspi_nor_config \
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flash_flexspi_nor_config_##n = { \
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.controller_label = DT_INST_BUS_LABEL(n), \
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.port = DT_INST_REG_ADDR(n), \
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.config = FLASH_FLEXSPI_DEVICE_CONFIG(n), \
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.layout = { \
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.pages_count = DT_INST_PROP(n, size) / 8 \
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/ SPI_NOR_SECTOR_SIZE, \
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.pages_size = SPI_NOR_SECTOR_SIZE, \
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}, \
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.flash_parameters = { \
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.write_block_size = NOR_WRITE_SIZE, \
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.erase_value = NOR_ERASE_VALUE, \
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}, \
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}; \
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\
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static struct flash_flexspi_nor_data \
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flash_flexspi_nor_data_##n; \
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\
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DEVICE_DT_INST_DEFINE(n, \
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flash_flexspi_nor_init, \
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NULL, \
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&flash_flexspi_nor_data_##n, \
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&flash_flexspi_nor_config_##n, \
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POST_KERNEL, \
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&flash_flexspi_nor_api);
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DT_INST_FOREACH_STATUS_OKAY(FLASH_FLEXSPI_NOR)
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