Kumar Gala e9a1d6493d dts: arm: nxp: imx: Use 'nxp,imx-{i,d}tcm' compatible ... On i.mx6/7 the TCMU and TCML regions are specific to instruction or data. So use the nxp,imx-itcm for TCML and nxp,imx-dtcm for TCMU. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>		2018-12-19 08:14:33 -06:00
..
nxp_imx6sx_m4.dtsi	dts: arm: nxp: imx: Use 'nxp,imx-{i,d}tcm' compatible	2018-12-19 08:14:33 -06:00
nxp_imx7d_m4.dtsi	dts: arm: nxp: imx: Use 'nxp,imx-{i,d}tcm' compatible	2018-12-19 08:14:33 -06:00
nxp_k6x.dtsi	dts: nxp: Add sram_l node to k64 dtsi	2018-12-17 08:20:29 -06:00
nxp_kl25z.dtsi	dts: Fix warnings associated with reg/unit-address not matching	2018-11-10 09:11:58 -05:00
nxp_kw2xd.dtsi	arm: kinetis: Add basic DTS support for RNGA	2018-11-06 08:49:50 -06:00
nxp_kw40z.dtsi	arm: kinetis: Add basic DTS support for TRNG	2018-11-06 08:49:50 -06:00
nxp_kw41z.dtsi	arm: kinetis: Add basic DTS support for TRNG	2018-11-06 08:49:50 -06:00
nxp_lpc54xxx.dtsi	dts: Fix warnings associated with reg/unit-address not matching	2018-11-10 09:11:58 -05:00
nxp_lpc54xxx_m0.dtsi	arch: arm: lpc: Added support for Cortex-M0+ on lpc54114 soc	2018-05-17 15:07:48 -05:00
nxp_lpc54xxx_m4.dtsi	arch: nxp: lpc54xxx: Rename SoC bits from LPC54114 to LPC54114_M4	2018-05-15 15:49:15 -05:00
nxp_rt.dtsi	dts: Rename imx-rt-{i,d}tcm compatible	2018-12-19 08:14:33 -06:00