161 lines
3.9 KiB
C
161 lines
3.9 KiB
C
/*
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* Copyright (c) 2022 IoT.bzh
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*
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* r8a7795 Clock Pulse Generator / Module Standby and Software Reset
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT renesas_r8a7795_cpg_mssr
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#include <errno.h>
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#include <soc.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/renesas_cpg_mssr.h>
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#include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
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#include <zephyr/dt-bindings/clock/r8a7795_cpg_mssr.h>
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#include "clock_control_renesas_cpg_mssr.h"
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#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(clock_control_rcar);
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struct r8a7795_cpg_mssr_config {
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mm_reg_t base_address;
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};
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int r8a7795_cpg_core_clock_endisable(uint32_t base_address, uint32_t module,
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uint32_t rate, bool enable)
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{
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uint32_t divider;
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unsigned int key;
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int ret = 0;
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/* Only support CANFD core clock at the moment */
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if (module != R8A7795_CLK_CANFD) {
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return -EINVAL;
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}
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key = irq_lock();
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if (enable) {
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if (rate > 0) {
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if ((CANFDCKCR_PARENT_CLK_RATE % rate) != 0) {
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LOG_ERR("Can not generate %u from CANFD parent clock", rate);
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ret = -EINVAL;
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goto unlock;
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}
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divider = (CANFDCKCR_PARENT_CLK_RATE / rate) - 1;
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if (divider > CANFDCKCR_DIVIDER_MASK) {
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LOG_ERR("Can not generate %u from CANFD parent clock", rate);
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ret = -EINVAL;
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goto unlock;
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}
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rcar_cpg_write(base_address, CANFDCKCR, divider);
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} else {
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LOG_ERR("Can not enable a clock at %u Hz", rate);
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ret = -EINVAL;
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}
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} else {
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rcar_cpg_write(base_address, CANFDCKCR, CANFDCKCR_CKSTP);
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}
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unlock:
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irq_unlock(key);
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return ret;
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}
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int r8a7795_cpg_mssr_start_stop(const struct device *dev, clock_control_subsys_t sys, bool enable)
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{
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const struct r8a7795_cpg_mssr_config *config = dev->config;
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struct rcar_cpg_clk *clk = (struct rcar_cpg_clk *)sys;
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int ret = -EINVAL;
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if (clk->domain == CPG_MOD) {
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ret = rcar_cpg_mstp_clock_endisable(config->base_address, clk->module, enable);
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} else if (clk->domain == CPG_CORE) {
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ret = r8a7795_cpg_core_clock_endisable(config->base_address, clk->module, clk->rate,
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enable);
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}
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return ret;
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}
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static int r8a7795_cpg_mssr_start(const struct device *dev,
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clock_control_subsys_t sys)
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{
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return r8a7795_cpg_mssr_start_stop(dev, sys, true);
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}
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static int r8a7795_cpg_mssr_stop(const struct device *dev,
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clock_control_subsys_t sys)
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{
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return r8a7795_cpg_mssr_start_stop(dev, sys, false);
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}
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static int r8a7795_cpg_get_rate(const struct device *dev,
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clock_control_subsys_t sys,
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uint32_t *rate)
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{
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const struct r8a7795_cpg_mssr_config *config = dev->config;
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struct rcar_cpg_clk *clk = (struct rcar_cpg_clk *)sys;
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uint32_t val;
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int ret = 0;
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if (clk->domain != CPG_CORE) {
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return -ENOTSUP;
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}
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switch (clk->module) {
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case R8A7795_CLK_CANFD:
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val = sys_read32(config->base_address + CANFDCKCR);
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if (val & CANFDCKCR_CKSTP) {
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*rate = 0;
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} else {
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val &= CANFDCKCR_DIVIDER_MASK;
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*rate = CANFDCKCR_PARENT_CLK_RATE / (val + 1);
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}
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break;
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case R8A7795_CLK_S3D4:
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*rate = S3D4_CLK_RATE;
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break;
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case R8A7795_CLK_S0D12:
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*rate = S0D12_CLK_RATE;
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break;
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default:
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ret = -ENOTSUP;
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break;
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}
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return ret;
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}
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static int r8a7795_cpg_mssr_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return 0;
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}
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static const struct clock_control_driver_api r8a7795_cpg_mssr_api = {
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.on = r8a7795_cpg_mssr_start,
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.off = r8a7795_cpg_mssr_stop,
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.get_rate = r8a7795_cpg_get_rate,
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};
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#define R8A7795_MSSR_INIT(inst) \
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static struct r8a7795_cpg_mssr_config r8a7795_cpg_mssr##inst##_config = { \
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.base_address = DT_INST_REG_ADDR(inst) \
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}; \
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\
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DEVICE_DT_INST_DEFINE(inst, \
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&r8a7795_cpg_mssr_init, \
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NULL, \
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NULL, &r8a7795_cpg_mssr##inst##_config, \
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PRE_KERNEL_1, \
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CONFIG_CLOCK_CONTROL_INIT_PRIORITY, \
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&r8a7795_cpg_mssr_api);
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DT_INST_FOREACH_STATUS_OKAY(R8A7795_MSSR_INIT)
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