477 lines
10 KiB
C
477 lines
10 KiB
C
/*
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* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file GPIO driver for the SiFive Freedom Processor
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*/
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#include <errno.h>
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#include <kernel.h>
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#include <device.h>
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#include <soc.h>
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#include <gpio.h>
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#include <misc/util.h>
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#include "gpio_utils.h"
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typedef void (*sifive_cfg_func_t)(void);
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/* sifive GPIO register-set structure */
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struct gpio_sifive_t {
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unsigned int in_val;
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unsigned int in_en;
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unsigned int out_en;
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unsigned int out_val;
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unsigned int pue;
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unsigned int ds;
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unsigned int rise_ie;
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unsigned int rise_ip;
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unsigned int fall_ie;
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unsigned int fall_ip;
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unsigned int high_ie;
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unsigned int high_ip;
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unsigned int low_ie;
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unsigned int low_ip;
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unsigned int iof_en;
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unsigned int iof_sel;
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unsigned int invert;
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};
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struct gpio_sifive_config {
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u32_t gpio_base_addr;
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u32_t gpio_irq_base;
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sifive_cfg_func_t gpio_cfg_func;
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};
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struct gpio_sifive_data {
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/* list of callbacks */
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sys_slist_t cb;
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};
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/* Helper Macros for GPIO */
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#define DEV_GPIO_CFG(dev) \
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((const struct gpio_sifive_config * const)(dev)->config->config_info)
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#define DEV_GPIO(dev) \
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((volatile struct gpio_sifive_t *)(DEV_GPIO_CFG(dev))->gpio_base_addr)
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#define DEV_GPIO_DATA(dev) \
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((struct gpio_sifive_data *)(dev)->driver_data)
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static void gpio_sifive_irq_handler(void *arg)
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{
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struct device *dev = (struct device *)arg;
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struct gpio_sifive_data *data = DEV_GPIO_DATA(dev);
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volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev);
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const struct gpio_sifive_config *cfg = DEV_GPIO_CFG(dev);
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int pin_mask;
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/* Get the pin number generating the interrupt */
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pin_mask = 1 << (riscv_plic_get_irq() -
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(cfg->gpio_irq_base - RISCV_MAX_GENERIC_IRQ));
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/* Call the corresponding callback registered for the pin */
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gpio_fire_callbacks(&data->cb, dev, pin_mask);
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/*
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* Write to either the rise_ip, fall_ip, high_ip or low_ip registers
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* to indicate to GPIO controller that interrupt for the corresponding
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* pin has been handled.
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*/
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if (gpio->rise_ip & pin_mask)
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gpio->rise_ip = pin_mask;
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else if (gpio->fall_ip & pin_mask)
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gpio->fall_ip = pin_mask;
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else if (gpio->high_ip & pin_mask)
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gpio->high_ip = pin_mask;
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else if (gpio->low_ip & pin_mask)
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gpio->low_ip = pin_mask;
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}
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/**
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* @brief Configure pin
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*
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* @param dev Device structure
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* @param access_op Access operation
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* @param pin The pin number
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* @param flags Flags of pin or port
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*
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* @return 0 if successful, failed otherwise
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*/
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static int gpio_sifive_config(struct device *dev,
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int access_op,
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u32_t pin,
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int flags)
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{
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volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev);
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if (access_op != GPIO_ACCESS_BY_PIN)
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return -ENOTSUP;
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if (pin >= SIFIVE_PINMUX_PINS)
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return -EINVAL;
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/* Configure gpio direction */
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if (flags & GPIO_DIR_OUT) {
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gpio->in_en &= ~BIT(pin);
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gpio->out_en |= BIT(pin);
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/*
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* Account for polarity only for GPIO_DIR_OUT.
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* invert register handles only output gpios
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*/
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if (flags & GPIO_POL_INV)
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gpio->invert |= BIT(pin);
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else
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gpio->invert &= ~BIT(pin);
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} else {
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gpio->out_en &= ~BIT(pin);
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gpio->in_en |= BIT(pin);
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/* Polarity inversion is not supported for input gpio */
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if (flags & GPIO_POL_INV)
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return -EINVAL;
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/*
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* Pull-up can be configured only for input gpios.
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* Only Pull-up can be enabled or disabled.
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*/
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if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_DOWN)
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return -EINVAL;
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if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_UP)
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gpio->pue |= BIT(pin);
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else
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gpio->pue &= ~BIT(pin);
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}
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/*
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* Configure interrupt if GPIO_INT is set.
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* Here, we just configure the gpio interrupt behavior,
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* we do not enable/disable interrupt for a particular
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* gpio.
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* Interrupt for a gpio is:
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* 1) enabled only via a call to gpio_sifive_enable_callback.
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* 2) disabled only via a call to gpio_sifive_disabled_callback.
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*/
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if (!(flags & GPIO_INT))
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return 0;
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/*
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* Interrupt cannot be set for GPIO_DIR_OUT
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*/
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if (flags & GPIO_DIR_OUT)
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return -EINVAL;
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/* Edge or Level triggered ? */
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if (flags & GPIO_INT_EDGE) {
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gpio->high_ie &= ~BIT(pin);
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gpio->low_ie &= ~BIT(pin);
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/* Rising Edge, Falling Edge or Double Edge ? */
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if (flags & GPIO_INT_DOUBLE_EDGE) {
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gpio->rise_ie |= BIT(pin);
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gpio->fall_ie |= BIT(pin);
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} else if (flags & GPIO_INT_ACTIVE_HIGH) {
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gpio->rise_ie |= BIT(pin);
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gpio->fall_ie &= ~BIT(pin);
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} else {
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gpio->rise_ie &= ~BIT(pin);
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gpio->fall_ie |= BIT(pin);
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}
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} else {
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gpio->rise_ie &= ~BIT(pin);
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gpio->fall_ie &= ~BIT(pin);
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/* Level High ? */
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if (flags & GPIO_INT_ACTIVE_HIGH) {
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gpio->high_ie |= BIT(pin);
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gpio->low_ie &= ~BIT(pin);
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} else {
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gpio->high_ie &= ~BIT(pin);
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gpio->low_ie |= BIT(pin);
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}
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}
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return 0;
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}
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/**
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* @brief Set the pin
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*
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* @param dev Device struct
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* @param access_op Access operation
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* @param pin The pin number
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* @param value Value to set (0 or 1)
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*
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* @return 0 if successful, failed otherwise
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*/
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static int gpio_sifive_write(struct device *dev,
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int access_op,
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u32_t pin,
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u32_t value)
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{
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volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev);
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if (access_op != GPIO_ACCESS_BY_PIN)
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return -ENOTSUP;
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if (pin >= SIFIVE_PINMUX_PINS)
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return -EINVAL;
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/* If pin is configured as input return with error */
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if (gpio->in_en & BIT(pin))
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return -EINVAL;
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if (value)
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gpio->out_val |= BIT(pin);
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else
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gpio->out_val &= ~BIT(pin);
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return 0;
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}
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/**
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* @brief Read the pin
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*
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* @param dev Device struct
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* @param access_op Access operation
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* @param pin The pin number
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* @param value Value of input pin(s)
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*
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* @return 0 if successful, failed otherwise
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*/
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static int gpio_sifive_read(struct device *dev,
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int access_op,
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u32_t pin,
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u32_t *value)
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{
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volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev);
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if (access_op != GPIO_ACCESS_BY_PIN)
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return -ENOTSUP;
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if (pin >= SIFIVE_PINMUX_PINS)
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return -EINVAL;
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/*
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* If gpio is configured as output,
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* read gpio value from out_val register,
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* otherwise read gpio value from in_val register
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*/
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if (gpio->out_en & BIT(pin))
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*value = !!(gpio->out_val & BIT(pin));
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else
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*value = !!(gpio->in_val & BIT(pin));
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return 0;
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}
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static int gpio_sifive_manage_callback(struct device *dev,
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struct gpio_callback *callback,
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bool set)
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{
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struct gpio_sifive_data *data = DEV_GPIO_DATA(dev);
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return gpio_manage_callback(&data->cb, callback, set);
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}
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static int gpio_sifive_enable_callback(struct device *dev,
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int access_op,
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u32_t pin)
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{
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const struct gpio_sifive_config *cfg = DEV_GPIO_CFG(dev);
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if (access_op != GPIO_ACCESS_BY_PIN)
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return -ENOTSUP;
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if (pin >= SIFIVE_PINMUX_PINS)
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return -EINVAL;
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/* Enable interrupt for the pin at PLIC level */
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irq_enable(cfg->gpio_irq_base + pin);
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return 0;
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}
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static int gpio_sifive_disable_callback(struct device *dev,
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int access_op,
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u32_t pin)
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{
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const struct gpio_sifive_config *cfg = DEV_GPIO_CFG(dev);
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if (access_op != GPIO_ACCESS_BY_PIN)
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return -ENOTSUP;
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if (pin >= SIFIVE_PINMUX_PINS)
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return -EINVAL;
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/* Disable interrupt for the pin at PLIC level */
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irq_disable(cfg->gpio_irq_base + pin);
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return 0;
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}
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static const struct gpio_driver_api gpio_sifive_driver = {
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.config = gpio_sifive_config,
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.write = gpio_sifive_write,
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.read = gpio_sifive_read,
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.manage_callback = gpio_sifive_manage_callback,
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.enable_callback = gpio_sifive_enable_callback,
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.disable_callback = gpio_sifive_disable_callback,
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};
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/**
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* @brief Initialize a GPIO controller
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*
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* Perform basic initialization of a GPIO controller
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*
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* @param dev GPIO device struct
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*
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* @return 0
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*/
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static int gpio_sifive_init(struct device *dev)
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{
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volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev);
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const struct gpio_sifive_config *cfg = DEV_GPIO_CFG(dev);
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/* Ensure that all gpio registers are reset to 0 initially */
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gpio->in_en = 0U;
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gpio->out_en = 0U;
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gpio->pue = 0U;
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gpio->rise_ie = 0U;
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gpio->fall_ie = 0U;
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gpio->high_ie = 0U;
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gpio->low_ie = 0U;
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gpio->invert = 0U;
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/* Setup IRQ handler for each gpio pin */
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cfg->gpio_cfg_func();
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return 0;
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}
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static void gpio_sifive_cfg_0(void);
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static const struct gpio_sifive_config gpio_sifive_config0 = {
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.gpio_base_addr = DT_SIFIVE_GPIO_0_BASE_ADDR,
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.gpio_irq_base = RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_0,
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.gpio_cfg_func = gpio_sifive_cfg_0,
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};
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static struct gpio_sifive_data gpio_sifive_data0;
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DEVICE_AND_API_INIT(gpio_sifive_0, CONFIG_GPIO_SIFIVE_GPIO_NAME,
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gpio_sifive_init,
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&gpio_sifive_data0, &gpio_sifive_config0,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&gpio_sifive_driver);
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#define IRQ_INIT(n) \
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IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_##n, \
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CONFIG_GPIO_SIFIVE_##n##_PRIORITY, \
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gpio_sifive_irq_handler, \
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DEVICE_GET(gpio_sifive_0), \
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0);
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static void gpio_sifive_cfg_0(void)
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{
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#ifdef DT_SIFIVE_GPIO_0_IRQ_0
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IRQ_INIT(0);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_1
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IRQ_INIT(1);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_2
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IRQ_INIT(2);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_3
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IRQ_INIT(3);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_4
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IRQ_INIT(4);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_5
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IRQ_INIT(5);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_6
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IRQ_INIT(6);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_7
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IRQ_INIT(7);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_8
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IRQ_INIT(8);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_9
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IRQ_INIT(9);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_10
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IRQ_INIT(10);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_11
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IRQ_INIT(11);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_12
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IRQ_INIT(12);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_13
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IRQ_INIT(13);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_14
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IRQ_INIT(14);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_15
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IRQ_INIT(15);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_16
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IRQ_INIT(16);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_17
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IRQ_INIT(17);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_18
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IRQ_INIT(18);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_19
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IRQ_INIT(19);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_20
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IRQ_INIT(20);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_21
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IRQ_INIT(21);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_22
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IRQ_INIT(22);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_23
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IRQ_INIT(23);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_24
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IRQ_INIT(24);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_25
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IRQ_INIT(25);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_26
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IRQ_INIT(26);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_27
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IRQ_INIT(27);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_28
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IRQ_INIT(28);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_29
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IRQ_INIT(29);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_30
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IRQ_INIT(30);
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#endif
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#ifdef DT_SIFIVE_GPIO_0_IRQ_31
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IRQ_INIT(31);
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#endif
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}
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