81 lines
1.6 KiB
Plaintext
81 lines
1.6 KiB
Plaintext
/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm64/armv8-a.dtsi>
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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#include <mem.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <3>;
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};
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};
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gic: interrupt-controller@1410000 {
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compatible = "arm,gic";
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reg = <0x01410000 0x10000>, /* GICD */
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<0x0142f000 0x1000>; /* GICC */
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interrupt-controller;
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#interrupt-cells = <4>;
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status = "okay";
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};
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psci: psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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sram0: memory@c0000000 {
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reg = <0xc0000000 DT_SIZE_M(1)>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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};
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uart1: serial@21c0600 {
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compatible = "fsl,ns16550", "ns16550";
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reg = <0x21c0600 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clock-frequency = <350000000>;
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reg-shift = <2>;
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status = "disabled";
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};
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};
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