618 lines
14 KiB
Plaintext
618 lines
14 KiB
Plaintext
/*
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* Copyright (c) 2021 The Chromium OS Authors
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* Copyright (c) 2021 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv8-m.dtsi>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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#include <zephyr/dt-bindings/clock/stm32u5_clock.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/flash_controller/ospi.h>
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#include <freq.h>
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/ {
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chosen {
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zephyr,entropy = &rng;
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zephyr,flash-controller = &flash;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m33";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8m-mpu";
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reg = <0xe000ed90 0x40>;
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arm,num-mpu-regions = <8>;
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};
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};
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "st,stm32-hse-clock";
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status = "disabled";
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(16)>;
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status = "disabled";
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};
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clk_msis: clk-msis {
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#clock-cells = <0>;
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compatible = "st,stm32u5-msi-clock";
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msi-range = <4>; /* 4MHz (reset value) */
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status = "disabled";
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};
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clk_msik: clk-msik {
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#clock-cells = <0>;
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compatible = "st,stm32u5-msi-clock";
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msi-range = <4>; /* 4MHz (reset value) */
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status = "disabled";
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};
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "st,stm32-lse-clock";
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clock-frequency = <32768>;
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driving-capability = <0>;
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status = "disabled";
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};
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clk_lsi: clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_K(32)>;
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status = "disabled";
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};
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pll1: pll: pll {
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#clock-cells = <0>;
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compatible = "st,stm32u5-pll-clock";
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status = "disabled";
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};
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pll2: pll2 {
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#clock-cells = <0>;
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compatible = "st,stm32u5-pll-clock";
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status = "disabled";
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};
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pll3: pll3 {
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#clock-cells = <0>;
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compatible = "st,stm32u5-pll-clock";
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status = "disabled";
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};
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};
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soc {
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flash: flash-controller@40022000 {
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compatible = "st,stm32-flash-controller", "st,stm32u5-flash-controller";
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reg = <0x40022000 0x400>;
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interrupts = <6 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@8000000 {
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compatible = "st,stm32-nv-flash", "soc-nv-flash";
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write-block-size = <16>;
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erase-block-size = <8192>;
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/* maximum erase time(ms) for a 8K sector */
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max-erase-time = <5>;
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};
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};
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rcc: rcc@46020c00 {
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compatible = "st,stm32u5-rcc";
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clocks-controller;
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#clock-cells = <2>;
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reg = <0x46020c00 0x400>;
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};
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exti: interrupt-controller@46022000 {
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compatible = "st,stm32-exti";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x46022000 0x400>;
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};
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pinctrl: pin-controller@42020000 {
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compatible = "st,stm32-pinctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x42020000 0x2000>;
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gpioa: gpio@42020000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42020000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>;
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};
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gpiob: gpio@42020400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42020400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>;
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};
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gpioc: gpio@42020800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42020800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000004>;
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};
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gpiod: gpio@42020c00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42020c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
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};
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gpioe: gpio@42021000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42021000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
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};
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gpiof: gpio@42021400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42021400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
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};
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gpiog: gpio@42021800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42021800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
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};
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gpioh: gpio@42021c00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42021c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>;
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};
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gpioi: gpio@42022000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x42022000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000100>;
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};
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};
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iwdg: watchdog@40003000 {
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compatible = "st,stm32-watchdog";
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reg = <0x40003000 0x400>;
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status = "disabled";
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};
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wwdg: wwdg1: watchdog@40002c00 {
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compatible = "st,stm32-window-watchdog";
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reg = <0x40002c00 0x1000>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
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interrupts = <0 7>;
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status = "disabled";
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};
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usart1: serial@40013800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40013800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
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interrupts = <61 0>;
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status = "disabled";
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};
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usart2: serial@40004400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
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interrupts = <62 0>;
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status = "disabled";
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};
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usart3: serial@40004800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
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interrupts = <63 0>;
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status = "disabled";
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};
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uart4: serial@40004c00 {
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compatible = "st,stm32-uart";
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reg = <0x40004c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
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interrupts = <64 0>;
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status = "disabled";
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};
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uart5: serial@40005000 {
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compatible = "st,stm32-uart";
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reg = <0x40005000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
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interrupts = <65 0>;
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status = "disabled";
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};
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lpuart1: serial@46002400 {
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compatible = "st,stm32-lpuart", "st,stm32-uart";
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reg = <0x46002400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000040>;
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interrupts = <66 0>;
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status = "disabled";
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};
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spi1: spi@40013000 {
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compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40013000 0x400>;
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interrupts = <59 5>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
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status = "disabled";
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};
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spi2: spi@40003800 {
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compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003800 0x400>;
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interrupts = <60 5>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
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status = "disabled";
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};
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spi3: spi@46002000 {
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compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x46002000 0x400>;
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interrupts = <99 5>;
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clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000020>;
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status = "disabled";
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};
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i2c1: i2c@40005400 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
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interrupts = <55 0>, <56 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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};
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i2c2: i2c@40005800 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
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interrupts = <57 0>, <58 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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};
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timers1: timers@40012c00 {
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compatible = "st,stm32-timers";
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reg = <0x40012c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
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interrupts = <41 0>, <42 0>, <43 0>, <44 0>;
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interrupt-names = "brk", "up", "trgcom", "cc";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers2: timers@40000000 {
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compatible = "st,stm32-timers";
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reg = <0x40000000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
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interrupts = <45 0>;
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interrupt-names = "global";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers3: timers@40000400 {
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compatible = "st,stm32-timers";
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reg = <0x40000400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
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interrupts = <46 0>;
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interrupt-names = "global";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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lptim1: timers@46004400 {
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compatible = "st,stm32-lptim";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x46004400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000800>;
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interrupts = <67 1>;
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interrupt-names = "wakeup";
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status = "disabled";
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};
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rtc: rtc@46007800 {
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compatible = "st,stm32-rtc";
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reg = <0x46007800 0x400>;
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interrupts = <2 0>;
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clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00200000>;
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prescaler = <32768>;
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status = "disabled";
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};
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timers4: timers@40000800 {
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compatible = "st,stm32-timers";
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reg = <0x40000800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
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interrupts = <47 0>;
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interrupt-names = "global";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers5: timers@40000c00 {
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compatible = "st,stm32-timers";
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reg = <0x40000c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
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interrupts = <48 0>;
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interrupt-names = "global";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers8: timers@40013400 {
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compatible = "st,stm32-timers";
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reg = <0x40013400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
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interrupts = <51 0>, <52 0>, <53 0>, <54 0>;
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interrupt-names = "brk", "up", "trgcom", "cc";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers15: timers@40014000 {
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compatible = "st,stm32-timers";
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reg = <0x40014000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
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interrupts = <69 0>;
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interrupt-names = "global";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers16: timers@40014400 {
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compatible = "st,stm32-timers";
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reg = <0x40014400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
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interrupts = <70 0>;
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interrupt-names = "global";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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timers17: timers@40014800 {
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compatible = "st,stm32-timers";
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reg = <0x40014800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
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interrupts = <71 0>;
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interrupt-names = "global";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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octospi1: octospi@420d1400 {
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compatible = "st,stm32-ospi";
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reg = <0x420d1400 0x400>;
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interrupts = <76 0>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2_2 0x00000010>,
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<&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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octospi2: octospi@420d2400 {
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compatible = "st,stm32-ospi";
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reg = <0x420d2400 0x400>;
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interrupts = <120 0>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2_2 0x00000100>,
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<&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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rng: rng@420c0800 {
|
|
compatible = "st,stm32-rng";
|
|
reg = <0x420c0800 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>;
|
|
interrupts = <94 0>;
|
|
nist-config = <0xf60d00>;
|
|
health-test-config = <0x9aae>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dac1: dac@46021800 {
|
|
compatible = "st,stm32-dac";
|
|
reg = <0x46021800 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000040>;
|
|
status = "disabled";
|
|
#io-channel-cells = <1>;
|
|
};
|
|
|
|
adc1: adc@42028000 {
|
|
compatible = "st,stm32-adc";
|
|
reg = <0x42028000 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000400>;
|
|
interrupts = <37 0>;
|
|
status = "disabled";
|
|
vref-mv = <3300>;
|
|
#io-channel-cells = <1>;
|
|
has-temp-channel;
|
|
has-vref-channel;
|
|
};
|
|
|
|
die_temp: dietemp {
|
|
compatible = "st,stm32-temp-cal";
|
|
ts-cal1-addr = <0x0BFA0710>;
|
|
ts-cal2-addr = <0x0BFA0742>;
|
|
ts-cal1-temp = <30>;
|
|
ts-cal2-temp = <130>;
|
|
ts-cal-vrefanalog = <3000>;
|
|
ts-cal-resolution = <14>;
|
|
io-channels = <&adc1 19>;
|
|
status = "disabled";
|
|
};
|
|
|
|
adc4: adc@46021000 {
|
|
compatible = "st,stm32-adc";
|
|
reg = <0x46021000 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000020>;
|
|
interrupts = <113 0>;
|
|
status = "disabled";
|
|
#io-channel-cells = <1>;
|
|
has-temp-channel;
|
|
has-vref-channel;
|
|
};
|
|
|
|
can {
|
|
compatible = "bosch,m_can-base";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
std-filter-elements = <28>;
|
|
ext-filter-elements = <8>;
|
|
rx-fifo0-elements = <3>;
|
|
rx-fifo1-elements = <3>;
|
|
rx-buffer-elements = <0>;
|
|
tx-buffer-elements = <3>;
|
|
|
|
can1: can@4000a400 {
|
|
compatible = "st,stm32-fdcan";
|
|
reg = <0x4000a400 0x400>, <0x4000ac00 0x350>;
|
|
reg-names = "m_can", "message_ram";
|
|
interrupts = <39 0>, <40 0>;
|
|
interrupt-names = "LINE_0", "LINE_1";
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>;
|
|
status = "disabled";
|
|
sjw = <1>;
|
|
sample-point = <875>;
|
|
sjw-data = <1>;
|
|
sample-point-data = <875>;
|
|
};
|
|
};
|
|
|
|
ucpd1: ucpd@4000dc00 {
|
|
compatible = "st,stm32-ucpd";
|
|
reg = <0x4000dc00 0x400>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
|
|
interrupts = <106 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gpdma1: dma@40020000 {
|
|
compatible = "st,stm32u5-dma";
|
|
#dma-cells = <3>;
|
|
reg = <0x40020000 0x400>;
|
|
interrupts = <29 0 30 0 31 0 32 0 33 0 34 0 35 0 36 0
|
|
80 0 81 0 82 0 83 0 84 0 85 0 86 0 87 0>;
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
|
|
dma-channels = <16>;
|
|
dma-requests = <114>;
|
|
dma-offset = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
&nvic {
|
|
arm,num-irq-priority-bits = <4>;
|
|
};
|