128 lines
3.1 KiB
Plaintext
128 lines
3.1 KiB
Plaintext
/*
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* Copyright (c) 2020 Alexander Kozhinov <AlexanderKozhinov@yandex.com>
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* Copyright (c) 2022 Georgij Cernysiov <geo.cgv@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <st/h7/stm32h7.dtsi>
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#include <zephyr/dt-bindings/display/stm32_ltdc.h>
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#include <zephyr/dt-bindings/flash_controller/ospi.h>
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/ {
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soc {
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flash-controller@52002000 {
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flash0: flash@8000000 {
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compatible = "st,stm32-nv-flash", "soc-nv-flash";
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write-block-size = <32>;
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erase-block-size = <DT_SIZE_K(128)>;
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/* maximum erase time for a 128K sector */
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max-erase-time = <4000>;
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};
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};
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uart9: serial@40011800 {
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compatible = "st,stm32-uart";
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reg = <0x40011800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000040>;
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interrupts = <155 0>;
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status = "disabled";
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};
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die_temp: dietemp {
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io-channels = <&adc3 17>;
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ts-cal2-temp = <130>;
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};
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usart10: serial@40011c00 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40011c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
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interrupts = <156 0>;
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status = "disabled";
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};
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dmamux1: dmamux@40020800 {
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dma-requests= <129>;
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};
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rng: rng@48021800 {
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health-test-magic = <0x17590abc>;
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health-test-config = <0xaa74>;
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};
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ltdc: display-controller@50001000 {
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compatible = "st,stm32-ltdc";
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reg = <0x50001000 0x200>;
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interrupts = <88 0>, <89 0>;
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interrupt-names = "ltdc", "ltdc_er";
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clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>;
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status = "disabled";
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};
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octospi1: octospi@52005000 {
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compatible = "st,stm32-ospi";
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reg = <0x52005000 0x1000>;
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interrupts = <92 0>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00004000>,
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<&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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octospi2: octospi@5200a000 {
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compatible = "st,stm32-ospi";
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reg = <0x5200a000 0x1000>;
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interrupts = <150 0>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x000080000>,
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<&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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/* D1 domain, AXI SRAM (128KB with shared ITCM 192KB as `TCM_AXI_SHARED` is `000`) */
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sram0: memory@24000000 {
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reg = <0x24000000 DT_SIZE_K(320)>;
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compatible = "mmio-sram";
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};
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/* D2 domain, AHB SRAM */
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sram1: memory@30000000 {
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reg = <0x30000000 DT_SIZE_K(16)>;
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compatible = "zephyr,memory-region", "mmio-sram";
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zephyr,memory-region = "SRAM1";
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};
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/* D2 domain, AHB SRAM */
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sram2: memory@30040000 {
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reg = <0x30040000 DT_SIZE_K(16)>;
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compatible = "zephyr,memory-region", "mmio-sram";
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zephyr,memory-region = "SRAM2";
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};
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/* D3 domain, AHB SRAM */
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sram4: memory@38000000 {
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reg = <0x38000000 DT_SIZE_K(16)>;
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compatible = "zephyr,memory-region", "mmio-sram";
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zephyr,memory-region = "SRAM4";
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};
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/* Data TCM RAM */
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dtcm: memory@20000000 {
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compatible = "zephyr,memory-region", "arm,dtcm";
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reg = <0x20000000 DT_SIZE_K(128)>;
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zephyr,memory-region = "DTCM";
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};
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/* Instruction TCM RAM (64KB as `TCM_AXI_SHARED` is `000`) */
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itcm: memory@0 {
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compatible = "zephyr,memory-region", "arm,itcm";
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reg = <0x00000000 DT_SIZE_K(64)>;
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zephyr,memory-region = "ITCM";
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};
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};
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