zephyr/dts/arm/st/f7/stm32f723.dtsi

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/*
* Copyright (c) 2018 Aurelien Jarno
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f7/stm32f7.dtsi>
/ {
/* 64KB DTCM @ 0x20000000, 176KB SRAM1 @ 0x20010000, 16KB SRAM2 @ 0x2003C00 */
sram0: memory@20010000 {
compatible = "mmio-sram";
reg = <0x20010000 DT_SIZE_K(192)>;
};
dtcm: memory@20000000 {
compatible = "zephyr,memory-region", "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(64)>;
zephyr,memory-region = "DTCM";
};
itcm: memory@0 {
compatible = "zephyr,memory-region", "arm,itcm";
reg = <0x00000000 DT_SIZE_K(16)>;
zephyr,memory-region = "ITCM";
};
soc {
usbphyc: usbphyc@40017c00 {
compatible = "st,stm32-usbphyc";
reg = <0x40017c00 0x400>;
#phy-cells = <0>;
};
usbotg_hs: usb@40040000 {
phys = <&usbphyc>;
maximum-speed = "high-speed";
};
sdmmc2: sdmmc@40011c00 {
compatible = "st,stm32-sdmmc";
reg = <0x40011c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
interrupts = <103 0>;
status = "disabled";
};
};
};
/delete-node/ &otghs_fs_phy;