zephyr/dts/arm/st/f3/stm32f373.dtsi

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/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f3/stm32f3.dtsi>
/ {
soc {
pinctrl: pin-controller@48000000 {
gpioe: gpio@48001000 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48001000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
};
};
i2c2: i2c@40005800 {
compatible = "st,stm32-i2c-v2";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
interrupts = <33 0>, <34 0>;
interrupt-names = "event", "error";
status = "disabled";
};
spi2: spi@40003800 {
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
interrupts = <36 5>;
status = "disabled";
};
spi3: spi@40003c00 {
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
interrupts = <51 5>;
status = "disabled";
};
timers4: timers@40000800 {
compatible = "st,stm32-timers";
reg = <0x40000800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
interrupts = <30 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
timers5: timers@40000c00 {
compatible = "st,stm32-timers";
reg = <0x40000c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
interrupts = <50 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
timers12: timers@40001800 {
compatible = "st,stm32-timers";
reg = <0x40001800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
interrupts = <43 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
timers13: timers@40001c00 {
compatible = "st,stm32-timers";
reg = <0x40001c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
interrupts = <44 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
timers14: timers@40002000 {
compatible = "st,stm32-timers";
reg = <0x40002000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
interrupts = <45 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
timers18: timers@40009c00 {
compatible = "st,stm32-timers";
reg = <0x40009c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000200>;
interrupts = <27 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
timers19: timers@40015c00 {
compatible = "st,stm32-timers";
reg = <0x40015c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00080000>;
interrupts = <78 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
adc1: adc@40012400 {
compatible = "st,stm32-adc";
reg = <0x40012400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
interrupts = <18 0>;
status = "disabled";
#io-channel-cells = <1>;
};
};
};