There're (at least) 2 UART TX interrupt causes: "tx fifo has more
room" and "transmission of tx fifo complete". Zephyr API has only
one function to enable TX interrupts, uart_irq_tx_enable(), so it's
fair to assume it enables interrupt for both conditions. But then
immediately after enabling TX IRQ, it will be fired with "tx fifo
has more room" cause. If ISR doesn't do anything to fill FIFO, on
some architectures, immediately after return from ISR, it will be
fired again (with no instruction progress in the main application
thread). That's exactly the situation with this test, and on ARM,
it leads to inifnite IRQ loop.
So, instead move call to uart_fifo_fill() inside ISR, and be sure
to disable TX IRQ after we transmitted enough characters.
Change-Id: Ibbd05acf96b01fdb128f08054819fd104d6dfae8
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
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