352 lines
12 KiB
C
352 lines
12 KiB
C
/*
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* Copyright (c) 2016 Cadence Design Systems, Inc.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <zephyr/types.h>
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#include <system_timer.h>
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#include <xtensa_rtos.h>
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#include <xtensa/tie/xt_timer.h>
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#include <xtensa_timer.h>
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#include "irq.h"
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#ifdef XT_BOARD
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#include <xtensa/xtbsp.h>
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#endif
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#include "xtensa_rtos.h"
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/*
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* This device driver can be also used with an extenal timer instead of
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* the internal one that may simply not exist.
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* The below macros are used to abstract the timer HW interface assuming that
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* it allows implementing them.
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* Of course depending on the HW specific requirements, part of the code may
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* need to changed. We tried to identify this code and hoghlight it to users.
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*
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* User shall track the TODO flags and follow the instruction to adapt the code
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* according to his HW.
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*/
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/* Abstraction macros to access the timer fire time register */
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#if CONFIG_XTENSA_INTERNAL_TIMER || (CONFIG_XTENSA_TIMER_IRQ < 0)
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#define _XT_SR_CCOMPARE(op, idx) XT_##op##SR_CCOMPARE##idx
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#define XT_SR_CCOMPARE(op, idx) _XT_SR_CCOMPARE(op, idx)
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/* Use XT_TIMER_INDEX to select XT_CHAL macro to access CCOMPAREx register */
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#define GET_TIMER_FIRE_TIME(void) XT_SR_CCOMPARE(R, XT_TIMER_INDEX)()
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#define SET_TIMER_FIRE_TIME(time) XT_SR_CCOMPARE(W, XT_TIMER_INDEX)(time)
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#define GET_TIMER_CURRENT_TIME(void) XT_RSR_CCOUNT()
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/* Value underwich, don't program next tick but trigger it immediately. */
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#define MIN_TIMER_PROG_DELAY 50
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#else /* Case of an external timer which is not emulated by internal timer */
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/* TODO: User who wants ot use and external timer should ensure that:
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* - CONFIG_XTENSA_INTERNAL_TIMER is unset
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* - CONFIG_XTENSA_TIMER_IRQ > 0
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* - Macros below are correctly implemented
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*/
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#define GET_TIMER_FIRE_TIME(void) /* TODO: Implement this case */
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#define SET_TIMER_FIRE_TIME(time) /* TODO: Implement this case */
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#define GET_TIMER_CURRENT_TIME(void) /* TODO: Implement this case */
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/* Value underwich, don't program next tick but trigger it immediately. */
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#define MIN_TIMER_PROG_DELAY 50 /* TODO: Update this value */
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#endif /* CONFIG_XTENSA_INTERNAL_TIMER || (CONFIG_XTENSA_TIMER_IRQ < 0) */
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#ifdef CONFIG_TICKLESS_IDLE
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#define TIMER_MODE_PERIODIC 0 /* normal running mode */
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#define TIMER_MODE_ONE_SHOT 1 /* emulated, since sysTick has 1 mode */
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#define IDLE_NOT_TICKLESS 0 /* non-tickless idle mode */
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#define IDLE_TICKLESS 1 /* tickless idle mode */
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extern s32_t _sys_idle_elapsed_ticks;
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static u32_t __noinit cycles_per_tick;
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static u32_t __noinit max_system_ticks;
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static u32_t idle_original_ticks;
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static u32_t __noinit max_load_value;
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static unsigned char timer_mode = TIMER_MODE_PERIODIC;
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static unsigned char idle_mode = IDLE_NOT_TICKLESS;
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static ALWAYS_INLINE void tickless_idle_init(void)
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{
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cycles_per_tick = sys_clock_hw_cycles_per_tick;
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/* calculate the max number of ticks with this 32-bit H/W counter */
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max_system_ticks = 0xffffffff / cycles_per_tick;
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max_load_value = max_system_ticks * cycles_per_tick;
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}
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/*
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* @brief Place the system timer into idle state
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*
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* Re-program the timer to enter into the idle state for either the given
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* number of ticks or the maximum number of ticks that can be programmed
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* into hardware.
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*
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* @return N/A
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*/
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void _timer_idle_enter(s32_t ticks)
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{
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u32_t P; /* Programming (current) time */
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u32_t F; /* Idle timer fire time */
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u32_t f; /* Last programmed timer fire time */
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if ((ticks == K_FOREVER) || (ticks > max_system_ticks)) {
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/*
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* The number of cycles until the timer must fire next might
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* not fit in the 32-bit counter register. To work around this,
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* program the counter to fire in the maximum number of ticks.
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*/
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idle_original_ticks = max_system_ticks - 1;
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} else {
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/* Leave one tick margin time to react when coming back */
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idle_original_ticks = ticks - 1;
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}
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/* Set timer to virtual "one shot" mode. */
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timer_mode = TIMER_MODE_ONE_SHOT;
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idle_mode = IDLE_TICKLESS;
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/*
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* We're being asked to have the timer fire in "ticks" from now. To
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* maintain accuracy we must account for the remaining time left in the
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* timer to the next tick to fire, so that the programmed fire time
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* corresponds always on a tick bondary.
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*/
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P = GET_TIMER_CURRENT_TIME();
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f = GET_TIMER_FIRE_TIME();
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/*
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* Get the time of last tick. As we are entring idle mode we are sure
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* that |f - P| < cycles_per_tick.
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* |-------f----P---|--------|--------|----F---|--------|--------|
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* |-------|----P---f--------|--------|----F---|--------|--------|
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* P f-----------s--------->F
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*/
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if (f < P) {
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f = f + cycles_per_tick;
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}
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F = f + idle_original_ticks * cycles_per_tick;
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/* Program the timer register to fire at the right time */
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SET_TIMER_FIRE_TIME(F);
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}
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/**
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*
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* @brief Handling of tickless idle when interrupted
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*
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* The routine, called by _sys_power_save_idle_exit, is responsible for taking
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* the timer out of idle mode and generating an interrupt at the next
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* tick interval. It is expected that interrupts have been disabled.
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* Note that in this routine, _sys_idle_elapsed_ticks must be zero because the
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* ticker has done its work and consumed all the ticks. This has to be true
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* otherwise idle mode wouldn't have been entered in the first place.
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*
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* @return N/A
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*/
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void _timer_idle_exit(void)
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{
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u32_t C; /* Current time (time within this function execution) */
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u32_t F; /* Idle timer programmed fire time */
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u32_t s; /* Requested idle timer sleep time */
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u32_t e; /* elapsed "Cer time" */
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u32_t r; /*reamining time to the timer to expire */
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if (timer_mode == TIMER_MODE_PERIODIC) {
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/*
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* The timer interrupt handler is handling a completed tickless
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* idle
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* or this has been called by mistake; there's nothing to do
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* here.
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*/
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return;
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}
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/*
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* This is a tricky logic where we use the particularity of unsigned
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* integers computation and overflow/underflow to check for timer expiry
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* In adddition to above defined variables, let's define following ones:
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* P := Programming time (time within _timer_idle_enter execution)
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* M := Maximum programmable value (0xFFFFFFFF)
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*
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* First case:
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0----fired---->P-----not fired---->F---------------fired------------M
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0 P<------------s-----F M
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0 P C<---r-----F M
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0 C<---------P-------------r-----F M
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0--------------P-------------r-----F C<----------------M
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*
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* Second case:
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0--not fired-->F-------fired------>P--------------not-fired---------M
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0--------s-----F P<-------------------------------M
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0--------r-----F C<---------P--------------------------------M
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0 C<---r-----F P M
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0--------r-----F P C<----------------M
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*
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* On both case, the timer fired when and only when r >= s.
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*/
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F = GET_TIMER_FIRE_TIME();
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s = idle_original_ticks * cycles_per_tick; /* also s = F - P; */
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C = GET_TIMER_CURRENT_TIME();
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r = F - C;
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/*
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* Announce elapsed ticks to the kernel. Note we are guaranteed
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* that the timer ISR will execute before the tick event is serviced,
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* so _sys_idle_elapsed_ticks is adjusted to account for it.
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*/
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e = s - r; /* also e = (C > P ? C - P : C - P + M); */
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_sys_idle_elapsed_ticks = e / cycles_per_tick;
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if (r >= s) {
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/*
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* The timer expired. There is nothing to do for this use case.
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* There is no need to reprogram the timer, the interrupt is
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* being serviced, and the timer ISR will be called after this
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* function returns.
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*/
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} else {
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/*
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* System was interrupted before the timer fires.
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* Reprogram to fire on tick edge: F := C + (r % cpt).
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*/
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F = C + (r - _sys_idle_elapsed_ticks * cycles_per_tick);
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C = GET_TIMER_CURRENT_TIME(); /* Update current time value */
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if (F - C < MIN_TIMER_PROG_DELAY) {
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/*
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* We are too close to the next tick edge. Let's fire
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* it manually and reprogram timer to fire on next one.
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*/
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F += cycles_per_tick;
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_sys_idle_elapsed_ticks += 1;
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}
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SET_TIMER_FIRE_TIME(F);
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}
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if (_sys_idle_elapsed_ticks) {
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_sys_clock_tick_announce();
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}
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/* Exit timer idle mode */
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idle_mode = IDLE_NOT_TICKLESS;
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timer_mode = TIMER_MODE_PERIODIC;
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}
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#endif /* CONFIG_TICKLESS_IDLE */
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#if CONFIG_XTENSA_INTERNAL_TIMER || (CONFIG_XTENSA_TIMER_IRQ < 0)
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// Internal timer
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extern void _zxt_tick_timer_init(void);
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unsigned int _xt_tick_divisor; /* cached number of cycles per tick */
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/*
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* Compute and initialize at run-time the tick divisor (the number of
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* processor clock cycles in an RTOS tick, used to set the tick timer).
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* Called when the processor clock frequency is not known at compile-time.
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*/
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void _xt_tick_divisor_init(void)
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{
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#ifdef XT_CLOCK_FREQ
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_xt_tick_divisor = (XT_CLOCK_FREQ / XT_TICK_PER_SEC);
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#else
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#ifdef XT_BOARD
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_xt_tick_divisor = xtbsp_clock_freq_hz() / XT_TICK_PER_SEC;
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#else
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#error "No way to obtain processor clock frequency"
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#endif /* XT_BOARD */
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#endif /* XT_CLOCK_FREQ */
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}
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#endif /* CONFIG_XTENSA_INTERNAL_TIMER || (CONFIG_XTENSA_TIMER_IRQ < 0) */
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/**
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*
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* @brief System clock tick handler
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*
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* This routine handles the system clock periodic tick interrupt. It always
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* announces one tick by pushing a TICK_EVENT event onto the kernel stack.
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*
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* @return N/A
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*/
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void _timer_int_handler(void *params)
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{
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ARG_UNUSED(params);
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#ifdef CONFIG_KERNEL_EVENT_LOGGER_INTERRUPT
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extern void _sys_k_event_logger_interrupt(void);
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_sys_k_event_logger_interrupt();
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#endif
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/* Announce the tick event to the kernel. */
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_sys_clock_final_tick_announce();
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}
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/**
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*
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* @brief Initialize and enable the system clock
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*
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* This routine is used to program the systick to deliver interrupts at the
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* rate specified via the 'sys_clock_us_per_tick' global variable.
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*
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* @return 0
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*/
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int _sys_clock_driver_init(struct device *device)
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{
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#if CONFIG_XTENSA_INTERNAL_TIMER || (CONFIG_XTENSA_TIMER_IRQ < 0)
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_xt_tick_divisor_init();
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/* Set up periodic tick timer (assume enough time to complete init). */
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_zxt_tick_timer_init();
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#else /* Case of an external timer which is not emulated by internal timer */
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/*
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* The code below is just an example code that is provided for Xtensa
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* customers as an example of how to support external timers.
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* The TODOs are here to tell customer what shall be re-implemented.
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* This implementation is not fake, it works with an external timer that
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* is provided as a systemC example and that could be plugged by using:
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* make run EMU_PLATFORM=xtsc-run.
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*
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*
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* The address below is that of the systemC timer example, provided in
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* ${ZEPHYR_BASE}/board/xt-sim/xtsc-models/external-irqs.
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* Hopefully, this hard-coded address doesn't conflict with anything
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* User needs for sure to rewrite this code to fit his timer.
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* I do agree that this hope is unlikely to be satisfied, but users who
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* don't have external timer will never hit here, and those who do, will
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* for sure modify this code in order to initialize their HW.
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*/
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/* TODO: Implement this case: remove below code and write yours */
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volatile u32_t *p_mmio = (u32_t *) 0xC0000000; /* start HW reg */
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u32_t interrupt = 0x00000000;
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/* Start the timer: Trigger the interrupt source drivers */
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*p_mmio = 0xFFFFFFFF;
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*p_mmio = interrupt;
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/*
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* Code above is example code, it is kept here on purpose to let users
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* find all code related to external timer support on the same file.
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* They will have to rewrite this anyway.
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*
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* Code below (enabling timer IRQ) is likely to reamin as is.
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*/
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/* Enable the interrupt handler */
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irq_enable(CONFIG_XTENSA_TIMER_IRQ);
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#endif /* CONFIG_XTENSA_INTERNAL_TIMER || (CONFIG_XTENSA_TIMER_IRQ < 0) */
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#if CONFIG_TICKLESS_IDLE
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tickless_idle_init();
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#endif
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return 0;
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}
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/**
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*
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* @brief Read the platform's timer hardware
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*
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* This routine returns the current time in terms of timer hardware clock
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* cycles.
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*
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* @return up counter of elapsed clock cycles
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*/
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u32_t _timer_cycle_get_32(void)
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{
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return GET_TIMER_CURRENT_TIME();
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}
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