Tomas Galbicka 069bcbcb7f drivers: mbox: Add NXP Mailbox driver for mbox ... This adds new NXP mailbox driver for MBOX device. NXP mailbox IP driver supports sending data between cores. It uses 32 bit register to trigger irq to other core. This driver implementation uses 4 bits for channel selection of triggering mode, 4 bits for channel selection of data transfer and rest 24 bits for data. NXP mailbox IP Reference Manual UM11126, Chapter 52. https://www.nxp.com/webapp/Download?colCode=UM11126 Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>		2024-02-02 09:31:33 -06:00
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CMakeLists.txt	drivers: mbox: Add NXP Mailbox driver for mbox	2024-02-02 09:31:33 -06:00
Kconfig	drivers: mbox: Add NXP Mailbox driver for mbox	2024-02-02 09:31:33 -06:00
Kconfig.andes	drivers: mbox: Add Andestech mailbox driver	2023-07-26 10:51:41 +02:00
Kconfig.nrfx	drivers: mbox: separate NRFx specific Kconfig	2023-01-24 14:37:20 +01:00
Kconfig.nxp_imx	mbox: Add NXP MU as a MBOX device	2023-09-14 14:34:05 +02:00
Kconfig.nxp_mailbox	drivers: mbox: Add NXP Mailbox driver for mbox	2024-02-02 09:31:33 -06:00
Kconfig.nxp_s32	drivers: select nocache only when supported	2023-09-26 15:09:51 +02:00
mbox_andes_plic_sw.c	arch: riscv: define RISC_IRQ_MSOFT/MEXT	2024-01-15 09:58:03 +01:00
mbox_handlers.c	syscall: rename Z_OOPS -> K_OOPS	2023-11-03 11:46:52 +01:00
mbox_nrfx_ipc.c	…
mbox_nxp_imx_mu.c	drivers: mbox: fix nxp mbox data read channel	2024-01-22 09:48:09 +00:00
mbox_nxp_mailbox.c	drivers: mbox: Add NXP Mailbox driver for mbox	2024-02-02 09:31:33 -06:00
mbox_nxp_s32_mru.c	drivers: mbox_nxp_s32_mru: update to RTD 1.0.0	2023-11-16 09:28:16 +01:00