zephyr/arch/xtensa/core
Lucas Tamborrino 9e289c1b20 arch: xtensa: save FPU register in context switching
Save FP user register and FP register file during context switch.

This change enables shared FP registers mode using CONFIG_FPU_SHARING.

Since there is no lazy stacking, the FPU registers will be saved regardless
of whether floating point calculations are performed in the threads when
CONFIG_FPU_SHARING is enabled. This require 72 additional bytes in the
stack memory.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2022-12-27 13:23:17 +01:00
..
include arch: xtensa: core: include: Update header to use guard macros 2022-07-20 13:39:23 -05:00
offsets
startup
CMakeLists.txt arch/xtensa: Add CCOUNT-based timing API 2022-06-07 19:04:42 +02:00
README-WINDOWS.rst
coredump.c debug: coredump: add xtensa intel adsp, support toolchains 2022-06-23 15:44:45 -04:00
cpu_idle.c
crt1.S
debug_helpers_asm.S
fatal.c debug: coredump: add xtensa intel adsp, support toolchains 2022-06-23 15:44:45 -04:00
gdbstub.c
gen_zsr.py
irq_manage.c
irq_offload.c include: add missing zephyr/irq.h include 2022-10-17 22:57:39 +09:00
timing.c includes: prefer <zephyr/kernel.h> over <zephyr/zephyr.h> 2022-09-05 16:31:47 +02:00
tls.c
window_vectors.S
xcc_stubs.c
xtensa-asm2-util.S arch: xtensa: save FPU register in context switching 2022-12-27 13:23:17 +01:00
xtensa-asm2.c arch: xtensa: implement ARCH_EXCEPT 2022-06-23 15:44:45 -04:00
xtensa_backtrace.c xtensa: use lower-case hex in backtrace output 2022-09-09 14:09:33 -05:00
xtensa_intgen.py include: add zephyr/ on script generated #include 2022-05-27 15:20:27 -07:00
xtensa_intgen.tmpl