zephyr/arch/x86/core
Carlo Caione 189cd1f4a2 cache: Rework cache API
The cache operations must be quick, optimized and possibly inlined. The
current API is clunky, functions are not inlined and passing parameters
around that are basically always known at compile time.

In this patch we rework the cache functions to allow us to get rid of
useless parameters and make inlining easier.

In particular this changeset is doing three things:

1. `CONFIG_HAS_ARCH_CACHE` is now `CONFIG_ARCH_CACHE` and
   `CONFIG_HAS_EXTERNAL_CACHE` is now `CONFIG_EXTERNAL_CACHE`

2. The cache API has been reworked.

3. Comments are added.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-12-01 13:40:56 -05:00
..
ia32 x86: buf return from gdb_reg_readone is not a string 2022-10-26 12:00:04 +02:00
intel64 arch: x86: Convert to CONFIG_MP_MAX_NUM_CPUS 2022-10-25 09:52:17 +03:00
offsets
CMakeLists.txt cache: Rework cache API 2022-12-01 13:40:56 -05:00
Kconfig.ia32
Kconfig.intel64
acpi.c
cache.c
common.S
cpuhalt.c
cpuid.c
early_serial.c drivers: pcie: reintroduce support for I/O BARs 2022-11-01 15:22:31 -04:00
efi.c
fatal.c
ia32.cmake
intel64.cmake
memmap.c
multiboot.c
pcie.c
prep_c.c smp: Move for loops to use arch_num_cpus instead of CONFIG_MP_NUM_CPUS 2022-10-21 13:14:58 +02:00
reboot_rst_cnt.c
spec_ctrl.c arch: x86: core: include kernel.h first 2022-10-11 18:05:17 +02:00
tls.c
userspace.c
x86_mmu.c