180 lines
4.1 KiB
C
180 lines
4.1 KiB
C
/*
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* Copyright (c) 2017-2018, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_lpc_mailbox
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#include <errno.h>
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#include <device.h>
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#include <drivers/ipm.h>
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#include <fsl_mailbox.h>
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#include <fsl_clock.h>
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#include <soc.h>
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#define MCUX_IPM_DATA_REGS 1
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#define MCUX_IPM_MAX_ID_VAL 0
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#if defined(__CM4_CMSIS_VERSION)
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#define MAILBOX_ID_THIS_CPU kMAILBOX_CM4
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#define MAILBOX_ID_OTHER_CPU kMAILBOX_CM0Plus
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#else
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#define MAILBOX_ID_THIS_CPU kMAILBOX_CM0Plus
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#define MAILBOX_ID_OTHER_CPU kMAILBOX_CM4
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#endif
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struct mcux_mailbox_config {
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MAILBOX_Type *base;
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void (*irq_config_func)(struct device *dev);
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};
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struct mcux_mailbox_data {
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ipm_callback_t callback;
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void *callback_ctx;
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};
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static void mcux_mailbox_isr(void *arg)
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{
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struct device *dev = arg;
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struct mcux_mailbox_data *data = dev->driver_data;
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const struct mcux_mailbox_config *config = dev->config_info;
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mailbox_cpu_id_t cpu_id;
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cpu_id = MAILBOX_ID_THIS_CPU;
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volatile uint32_t value = MAILBOX_GetValue(config->base, cpu_id);
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__ASSERT(value, "spurious MAILBOX interrupt");
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/* Clear or the interrupt gets called intermittently */
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MAILBOX_ClearValueBits(config->base, cpu_id, value);
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if (data->callback) {
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/* Only one MAILBOX, id is unused and set to 0 */
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data->callback(data->callback_ctx, 0, &value);
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}
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/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F
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* Store immediate overlapping exception return operation
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* might vector to incorrect interrupt
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*/
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#if defined __CORTEX_M && (__CORTEX_M == 4U)
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__DSB();
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#endif
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}
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static int mcux_mailbox_ipm_send(struct device *d, int wait, uint32_t id,
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const void *data, int size)
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{
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const struct mcux_mailbox_config *config = d->config_info;
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MAILBOX_Type *base = config->base;
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uint32_t data32[MCUX_IPM_DATA_REGS]; /* Until we change API
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* to uint32_t array
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*/
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unsigned int flags;
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int i;
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ARG_UNUSED(wait);
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if (id > MCUX_IPM_MAX_ID_VAL) {
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return -EINVAL;
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}
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if (size > MCUX_IPM_DATA_REGS * sizeof(uint32_t)) {
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return -EMSGSIZE;
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}
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flags = irq_lock();
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/* Actual message is passing using 32 bits registers */
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memcpy(data32, data, size);
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for (i = 0; i < ARRAY_SIZE(data32); ++i) {
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MAILBOX_SetValueBits(base, MAILBOX_ID_OTHER_CPU, data32[i]);
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}
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irq_unlock(flags);
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return 0;
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}
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static int mcux_mailbox_ipm_max_data_size_get(struct device *d)
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{
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ARG_UNUSED(d);
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/* Only a single 32-bit register available */
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return MCUX_IPM_DATA_REGS*sizeof(uint32_t);
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}
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static uint32_t mcux_mailbox_ipm_max_id_val_get(struct device *d)
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{
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ARG_UNUSED(d);
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/* Only a single instance of MAILBOX available for this platform */
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return MCUX_IPM_MAX_ID_VAL;
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}
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static void mcux_mailbox_ipm_register_callback(struct device *d,
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ipm_callback_t cb,
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void *context)
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{
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struct mcux_mailbox_data *driver_data = d->driver_data;
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driver_data->callback = cb;
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driver_data->callback_ctx = context;
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}
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static int mcux_mailbox_ipm_set_enabled(struct device *d, int enable)
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{
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/* For now: nothing to be done */
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return 0;
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}
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static int mcux_mailbox_init(struct device *dev)
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{
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const struct mcux_mailbox_config *config = dev->config_info;
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MAILBOX_Init(config->base);
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config->irq_config_func(dev);
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return 0;
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}
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static const struct ipm_driver_api mcux_mailbox_driver_api = {
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.send = mcux_mailbox_ipm_send,
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.register_callback = mcux_mailbox_ipm_register_callback,
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.max_data_size_get = mcux_mailbox_ipm_max_data_size_get,
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.max_id_val_get = mcux_mailbox_ipm_max_id_val_get,
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.set_enabled = mcux_mailbox_ipm_set_enabled
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};
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/* Config MAILBOX 0 */
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static void mcux_mailbox_config_func_0(struct device *dev);
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static const struct mcux_mailbox_config mcux_mailbox_0_config = {
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.base = (MAILBOX_Type *)DT_INST_REG_ADDR(0),
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.irq_config_func = mcux_mailbox_config_func_0,
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};
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static struct mcux_mailbox_data mcux_mailbox_0_data;
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DEVICE_AND_API_INIT(mailbox_0, DT_INST_LABEL(0),
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&mcux_mailbox_init,
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&mcux_mailbox_0_data, &mcux_mailbox_0_config,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&mcux_mailbox_driver_api);
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static void mcux_mailbox_config_func_0(struct device *dev)
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{
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IRQ_CONNECT(DT_INST_IRQN(0),
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DT_INST_IRQ(0, priority),
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mcux_mailbox_isr, DEVICE_GET(mailbox_0), 0);
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irq_enable(DT_INST_IRQN(0));
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}
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