133 lines
3.3 KiB
C
133 lines
3.3 KiB
C
/*
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* Copyright (c) 2017 comsuisse AG
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/** @file
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* @brief Atmel SAM MCU family Direct Memory Access (XDMAC) driver.
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*/
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#ifndef ZEPHYR_DRIVERS_DMA_DMA_SAM_XDMAC_H_
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#define ZEPHYR_DRIVERS_DMA_DMA_SAM_XDMAC_H_
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** DMA transfer callback */
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typedef void (*dma_callback)(void *arg, uint32_t channel, int error_code);
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/* XDMA_MBR_UBC */
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#define XDMA_UBC_NDE (0x1u << 24)
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#define XDMA_UBC_NDE_FETCH_DIS (0x0u << 24)
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#define XDMA_UBC_NDE_FETCH_EN (0x1u << 24)
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#define XDMA_UBC_NSEN (0x1u << 25)
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#define XDMA_UBC_NSEN_UNCHANGED (0x0u << 25)
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#define XDMA_UBC_NSEN_UPDATED (0x1u << 25)
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#define XDMA_UBC_NDEN (0x1u << 26)
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#define XDMA_UBC_NDEN_UNCHANGED (0x0u << 26)
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#define XDMA_UBC_NDEN_UPDATED (0x1u << 26)
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#define XDMA_UBC_NVIEW_SHIFT 27
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#define XDMA_UBC_NVIEW_MASK (0x3u << XDMA_UBC_NVIEW_SHIFT)
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#define XDMA_UBC_NVIEW_NDV0 (0x0u << XDMA_UBC_NVIEW_SHIFT)
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#define XDMA_UBC_NVIEW_NDV1 (0x1u << XDMA_UBC_NVIEW_SHIFT)
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#define XDMA_UBC_NVIEW_NDV2 (0x2u << XDMA_UBC_NVIEW_SHIFT)
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#define XDMA_UBC_NVIEW_NDV3 (0x3u << XDMA_UBC_NVIEW_SHIFT)
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/** DMA channel configuration parameters */
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struct sam_xdmac_channel_config {
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/** Configuration Register */
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uint32_t cfg;
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/** Data Stride / Memory Set Pattern Register */
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uint32_t ds_msp;
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/** Source Microblock Stride */
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uint32_t sus;
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/** Destination Microblock Stride */
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uint32_t dus;
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/** Channel Interrupt Enable */
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uint32_t cie;
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};
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/** DMA transfer configuration parameters */
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struct sam_xdmac_transfer_config {
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/** Microblock length */
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uint32_t ublen;
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/** Source Address */
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uint32_t sa;
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/** Destination Address */
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uint32_t da;
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/** Block length (The length of the block is (blen+1) microblocks) */
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uint32_t blen;
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/** Next descriptor address */
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uint32_t nda;
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/** Next descriptor configuration */
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uint32_t ndc;
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};
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/** DMA Master transfer linked list view 0 structure */
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struct sam_xdmac_linked_list_desc_view0 {
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/** Next Descriptor Address */
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uint32_t mbr_nda;
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/** Microblock Control */
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uint32_t mbr_ubc;
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/** Transfer Address */
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uint32_t mbr_ta;
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};
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/** DMA Master transfer linked list view 1 structure */
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struct sam_xdmac_linked_list_desc_view1 {
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/** Next Descriptor Address */
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uint32_t mbr_nda;
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/** Microblock Control */
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uint32_t mbr_ubc;
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/** Source Address */
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uint32_t mbr_sa;
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/** Destination Address */
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uint32_t mbr_da;
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};
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/** DMA Master transfer linked list view 2 structure */
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struct sam_xdmac_linked_list_desc_view2 {
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/** Next Descriptor Address */
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uint32_t mbr_nda;
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/** Microblock Control */
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uint32_t mbr_ubc;
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/** Source Address */
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uint32_t mbr_sa;
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/** Destination Address */
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uint32_t mbr_da;
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/** Configuration Register */
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uint32_t mbr_cfg;
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};
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/** DMA Master transfer linked list view 3 structure */
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struct sam_xdmac_linked_list_desc_view3 {
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/** Next Descriptor Address */
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uint32_t mbr_nda;
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/** Microblock Control */
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uint32_t mbr_ubc;
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/** Source Address */
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uint32_t mbr_sa;
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/** Destination Address */
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uint32_t mbr_da;
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/** Configuration Register */
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uint32_t mbr_cfg;
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/** Block Control */
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uint32_t mbr_bc;
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/** Data Stride */
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uint32_t mbr_ds;
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/** Source Microblock Stride */
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uint32_t mbr_sus;
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/** Destination Microblock Stride */
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uint32_t mbr_dus;
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_DRIVERS_DMA_DMA_SAM_XDMAC_H_ */
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