175 lines
4.5 KiB
C
175 lines
4.5 KiB
C
/*
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* Copyright (c) 2014-2015 Wind River Systems, Inc.
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright (c) 2017, Phytec Messtechnik GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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#include <drivers/uart.h>
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#include <fsl_common.h>
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#include <fsl_clock.h>
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#include <arch/cpu.h>
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#include <cortex_m/exc.h>
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#define PLLFLLSEL_MCGFLLCLK (0)
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#define PLLFLLSEL_MCGPLLCLK (1)
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#define PLLFLLSEL_IRC48MHZ (3)
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#define ER32KSEL_OSC32KCLK (0)
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#define ER32KSEL_RTC (2)
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#define ER32KSEL_LPO1KHZ (3)
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#define TIMESRC_OSCERCLK (2)
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static const osc_config_t oscConfig = {
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.freq = CONFIG_OSC_XTAL0_FREQ,
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.capLoad = 0,
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#if defined(CONFIG_OSC_EXTERNAL)
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.workMode = kOSC_ModeExt,
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#elif defined(CONFIG_OSC_LOW_POWER)
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.workMode = kOSC_ModeOscLowPower,
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#elif defined(CONFIG_OSC_HIGH_GAIN)
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.workMode = kOSC_ModeOscHighGain,
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#else
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#error "An oscillator mode must be defined"
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#endif
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.oscerConfig = {
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.enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop,
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#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && \
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FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
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.erclkDiv = 0U,
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#endif
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},
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};
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static const mcg_pll_config_t pll0Config = {
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.enableMode = 0U,
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.prdiv = CONFIG_MCG_PRDIV0,
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.vdiv = CONFIG_MCG_VDIV0,
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};
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static const sim_clock_config_t simConfig = {
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.pllFllSel = PLLFLLSEL_MCGPLLCLK, /* PLLFLLSEL select PLL. */
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.er32kSrc = ER32KSEL_RTC, /* ERCLK32K selection, use RTC. */
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.clkdiv1 = SIM_CLKDIV1_OUTDIV1(CONFIG_KW2XD_CORE_CLOCK_DIVIDER - 1) |
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SIM_CLKDIV1_OUTDIV2(CONFIG_KW2XD_BUS_CLOCK_DIVIDER - 1) |
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SIM_CLKDIV1_OUTDIV4(CONFIG_KW2XD_FLASH_CLOCK_DIVIDER - 1),
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};
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/**
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*
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* @brief Initialize radio transceiver clock output
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*
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* The clock output of the transceiver can be used as an input clock
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* for the PLL of the SoC. The clock output (CLK_OUT) is internally connected
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* to the input pin EXTAL0 of the SoC. This routine will initialize the clock
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* output of the transceiver at 4 MHz. The default frequency of the CLK_OUT
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* depends on the state of GPIO5 during transceiver reset. The frequency
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* will be 4 MHz if the GPIO5 pin is low, otherwise it will be 32.78689 kHz.
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*
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* @return N/A
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*
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*/
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static void set_modem_clock(void)
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{
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/* Ungate PORTB and PORTC clock */
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SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK;
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/* Set PORTB.19 as output - modem RESET pin */
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GPIOB->PDDR |= 0x00080000u;
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/* Set PORTC.0 as output - modem GPIO5 pin */
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GPIOC->PDDR |= 0x00000001u;
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/* PORTB.19 as GPIO */
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PORTB->PCR[19] = (PORTB->PCR[19] & ~PORT_PCR_MUX_MASK) |
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PORT_PCR_MUX(0x01u);
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/* PORTC.0 as GPIO */
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PORTC->PCR[0] = (PORTC->PCR[0] & ~PORT_PCR_MUX_MASK) |
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PORT_PCR_MUX(0x01u);
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/* Clear modem GPIO5 pin */
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GPIOC->PCOR = 0x00000001u;
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/* Clear modem RESET pin */
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GPIOB->PCOR = 0x00080000u;
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/* Set modem RESET pin */
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GPIOB->PSOR = 0x00080000u;
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}
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/**
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*
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* @brief Initialize the system clock
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*
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* This routine will configure the multipurpose clock generator (MCG) to
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* set up the system clock.
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* The MCG has nine possible modes, including Stop mode. This routine assumes
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* that the current MCG mode is FLL Engaged Internal (FEI), as from reset.
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* It transitions through the FLL Bypassed External (FBE) and
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* PLL Bypassed External (PBE) modes to get to the desired
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* PLL Engaged External (PEE) mode and generate the maximum 48 MHz system
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* clock.
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*
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* @return N/A
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*
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*/
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static ALWAYS_INLINE void clock_init(void)
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{
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CLOCK_SetSimSafeDivs();
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set_modem_clock();
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CLOCK_InitOsc0(&oscConfig);
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CLOCK_SetXtal0Freq(CONFIG_OSC_XTAL0_FREQ);
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CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
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CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow,
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CONFIG_MCG_FCRDIV);
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CLOCK_SetSimConfig(&simConfig);
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#if CONFIG_USB_KINETIS
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CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0,
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DT_ARM_CORTEX_M4_0_CLOCK_FREQUENCY);
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#endif
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}
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/**
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*
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* @brief Perform basic hardware initialization
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*
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* Initialize the interrupt controller device drivers.
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* Also initialize the timer device driver, if required.
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*
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* @return 0
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*/
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static int kw2xd_init(struct device *arg)
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{
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ARG_UNUSED(arg);
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unsigned int oldLevel; /* old interrupt lock level */
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/* disable interrupts */
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oldLevel = irq_lock();
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/* release I/O power hold to allow normal run state */
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PMC->REGSC |= PMC_REGSC_ACKISO_MASK;
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/* Initialize PLL/system clock to 48 MHz */
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clock_init();
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/*
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* install default handler that simply resets the CPU
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* if configured in the kernel, NOP otherwise
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*/
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NMI_INIT();
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/* restore interrupt state */
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irq_unlock(oldLevel);
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return 0;
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}
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SYS_INIT(kw2xd_init, PRE_KERNEL_1, 0);
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