355 lines
8.1 KiB
Plaintext
355 lines
8.1 KiB
Plaintext
# Kconfig - i.MX RT series
|
|
#
|
|
# Copyright (c) 2017, NXP
|
|
#
|
|
# SPDX-License-Identifier: Apache-2.0
|
|
#
|
|
|
|
choice
|
|
prompt "i.MX RT Selection"
|
|
depends on SOC_SERIES_IMX_RT
|
|
|
|
config SOC_MIMXRT1015
|
|
bool "SOC_MIMXRT1015"
|
|
select HAS_MCUX
|
|
select HAS_MCUX_CACHE
|
|
select HAS_MCUX_CCM
|
|
select HAS_MCUX_IGPIO
|
|
select HAS_MCUX_LPI2C
|
|
select HAS_MCUX_LPSPI
|
|
select HAS_MCUX_LPUART
|
|
select HAS_MCUX_GPT
|
|
select HAS_MCUX_TRNG
|
|
select CPU_HAS_FPU_DOUBLE_PRECISION
|
|
select CPU_HAS_ARM_MPU
|
|
select INIT_SYS_PLL
|
|
select INIT_USB1_PLL
|
|
select INIT_ENET_PLL
|
|
select HAS_MCUX_USB_EHCI
|
|
select HAS_MCUX_USDHC1
|
|
select HAS_MCUX_USDHC2
|
|
|
|
config SOC_MIMXRT1021
|
|
bool "SOC_MIMXRT1021"
|
|
select HAS_MCUX
|
|
select HAS_MCUX_CACHE
|
|
select HAS_MCUX_CCM
|
|
select HAS_MCUX_ENET
|
|
select HAS_MCUX_IGPIO
|
|
select HAS_MCUX_LPI2C
|
|
select HAS_MCUX_LPSPI
|
|
select HAS_MCUX_LPUART
|
|
select HAS_MCUX_GPT
|
|
select HAS_MCUX_TRNG
|
|
select CPU_HAS_FPU_DOUBLE_PRECISION
|
|
select CPU_HAS_ARM_MPU
|
|
select INIT_SYS_PLL
|
|
select INIT_USB1_PLL
|
|
select INIT_ENET_PLL
|
|
select HAS_MCUX_USB_EHCI
|
|
select HAS_MCUX_USDHC1
|
|
select HAS_MCUX_USDHC2
|
|
|
|
config SOC_MIMXRT1051
|
|
bool "SOC_MIMXRT1051"
|
|
select HAS_MCUX
|
|
select HAS_MCUX_CACHE
|
|
select HAS_MCUX_CCM
|
|
select HAS_MCUX_ENET
|
|
select HAS_MCUX_IGPIO
|
|
select HAS_MCUX_LPI2C
|
|
select HAS_MCUX_LPSPI
|
|
select HAS_MCUX_LPUART
|
|
select HAS_MCUX_GPT
|
|
select HAS_MCUX_TRNG
|
|
select CPU_HAS_FPU_DOUBLE_PRECISION
|
|
select CPU_HAS_ARM_MPU
|
|
select INIT_ARM_PLL
|
|
select INIT_SYS_PLL
|
|
select INIT_USB1_PLL
|
|
select HAS_MCUX_USB_EHCI
|
|
select HAS_MCUX_USDHC1
|
|
select HAS_MCUX_USDHC2
|
|
|
|
config SOC_MIMXRT1052
|
|
bool "SOC_MIMXRT1052"
|
|
select HAS_MCUX
|
|
select HAS_MCUX_CACHE
|
|
select HAS_MCUX_CCM
|
|
select HAS_MCUX_ELCDIF
|
|
select HAS_MCUX_ENET
|
|
select HAS_MCUX_IGPIO
|
|
select HAS_MCUX_LPI2C
|
|
select HAS_MCUX_LPSPI
|
|
select HAS_MCUX_LPUART
|
|
select HAS_MCUX_GPT
|
|
select HAS_MCUX_TRNG
|
|
select CPU_HAS_FPU_DOUBLE_PRECISION
|
|
select CPU_HAS_ARM_MPU
|
|
select INIT_ARM_PLL
|
|
select INIT_SYS_PLL
|
|
select INIT_USB1_PLL
|
|
select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF
|
|
select HAS_MCUX_USB_EHCI
|
|
select HAS_MCUX_USDHC1
|
|
select HAS_MCUX_USDHC2
|
|
|
|
config SOC_MIMXRT1061
|
|
bool "SOC_MIMXRT1061"
|
|
select HAS_MCUX
|
|
select HAS_MCUX_CACHE
|
|
select HAS_MCUX_CCM
|
|
select HAS_MCUX_ENET
|
|
select HAS_MCUX_IGPIO
|
|
select HAS_MCUX_LPI2C
|
|
select HAS_MCUX_LPUART
|
|
select HAS_MCUX_GPT
|
|
select HAS_MCUX_TRNG
|
|
select CPU_HAS_FPU_DOUBLE_PRECISION
|
|
select CPU_HAS_ARM_MPU
|
|
select INIT_ARM_PLL
|
|
select INIT_SYS_PLL
|
|
select INIT_USB1_PLL
|
|
select HAS_MCUX_USB_EHCI
|
|
select HAS_MCUX_USDHC1
|
|
select HAS_MCUX_USDHC2
|
|
|
|
config SOC_MIMXRT1062
|
|
bool "SOC_MIMXRT1062"
|
|
select HAS_MCUX
|
|
select HAS_MCUX_CACHE
|
|
select HAS_MCUX_CCM
|
|
select HAS_MCUX_ELCDIF
|
|
select HAS_MCUX_ENET
|
|
select HAS_MCUX_PWM
|
|
select HAS_MCUX_IGPIO
|
|
select HAS_MCUX_LPI2C
|
|
select HAS_MCUX_LPUART
|
|
select HAS_MCUX_GPT
|
|
select HAS_MCUX_TRNG
|
|
select CPU_HAS_FPU_DOUBLE_PRECISION
|
|
select CPU_HAS_ARM_MPU
|
|
select INIT_ARM_PLL
|
|
select INIT_SYS_PLL
|
|
select INIT_USB1_PLL
|
|
select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF
|
|
select HAS_MCUX_USB_EHCI
|
|
select HAS_MCUX_USDHC1
|
|
select HAS_MCUX_USDHC2
|
|
|
|
config SOC_MIMXRT1064
|
|
bool "SOC_MIMXRT1064"
|
|
select HAS_MCUX
|
|
select HAS_MCUX_CACHE
|
|
select HAS_MCUX_CCM
|
|
select HAS_MCUX_ELCDIF
|
|
select HAS_MCUX_ENET
|
|
select HAS_MCUX_PWM
|
|
select HAS_MCUX_IGPIO
|
|
select HAS_MCUX_LPI2C
|
|
select HAS_MCUX_LPUART
|
|
select HAS_MCUX_GPT
|
|
select HAS_MCUX_TRNG
|
|
select CPU_HAS_FPU_DOUBLE_PRECISION
|
|
select CPU_HAS_ARM_MPU
|
|
select INIT_ARM_PLL
|
|
select INIT_SYS_PLL
|
|
select INIT_USB1_PLL
|
|
select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF
|
|
select HAS_MCUX_USB_EHCI
|
|
select HAS_MCUX_USDHC1
|
|
select HAS_MCUX_USDHC2
|
|
|
|
endchoice
|
|
|
|
if SOC_SERIES_IMX_RT
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1015CAF4A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1015DAF5A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1021CAF4A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1021CAG4A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1021DAF5A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1021DAG5A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1051CVL5A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1051DVL6A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1052CVJ5B
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1052CVL5A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1052CVL5B
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1052DVJ6B
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1052DVL6A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1052DVL6B
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1061CVL5A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1061DVL6A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1062CVL5A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1062DVL6A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1064CVL5A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1064DVL6A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_IMX_RT
|
|
string
|
|
default "MIMXRT1015CAF4A" if SOC_PART_NUMBER_MIMXRT1015CAF4A
|
|
default "MIMXRT1015DAF5A" if SOC_PART_NUMBER_MIMXRT1015DAF5A
|
|
default "MIMXRT1021CAF4A" if SOC_PART_NUMBER_MIMXRT1021CAF4A
|
|
default "MIMXRT1021CAG4A" if SOC_PART_NUMBER_MIMXRT1021CAG4A
|
|
default "MIMXRT1021DAF5A" if SOC_PART_NUMBER_MIMXRT1021DAF5A
|
|
default "MIMXRT1021DAG5A" if SOC_PART_NUMBER_MIMXRT1021DAG5A
|
|
default "MIMXRT1051CVL5A" if SOC_PART_NUMBER_MIMXRT1051CVL5A
|
|
default "MIMXRT1051DVL6A" if SOC_PART_NUMBER_MIMXRT1051DVL6A
|
|
default "MIMXRT1052CVJ5B" if SOC_PART_NUMBER_MIMXRT1052CVJ5B
|
|
default "MIMXRT1052CVL5A" if SOC_PART_NUMBER_MIMXRT1052CVL5A
|
|
default "MIMXRT1052CVL5B" if SOC_PART_NUMBER_MIMXRT1052CVL5B
|
|
default "MIMXRT1052DVJ6B" if SOC_PART_NUMBER_MIMXRT1052DVJ6B
|
|
default "MIMXRT1052DVL6A" if SOC_PART_NUMBER_MIMXRT1052DVL6A
|
|
default "MIMXRT1052DVL6B" if SOC_PART_NUMBER_MIMXRT1052DVL6B
|
|
default "MIMXRT1061CVL5A" if SOC_PART_NUMBER_MIMXRT1061CVL5A
|
|
default "MIMXRT1061DVL6A" if SOC_PART_NUMBER_MIMXRT1061DVL6A
|
|
default "MIMXRT1062CVL5A" if SOC_PART_NUMBER_MIMXRT1062CVL5A
|
|
default "MIMXRT1062DVL6A" if SOC_PART_NUMBER_MIMXRT1062DVL6A
|
|
default "MIMXRT1064CVL5A" if SOC_PART_NUMBER_MIMXRT1064CVL5A
|
|
default "MIMXRT1064DVL6A" if SOC_PART_NUMBER_MIMXRT1064DVL6A
|
|
help
|
|
This string holds the full part number of the SoC. It is a hidden option
|
|
that you should not set directly. The part number selection choice defines
|
|
the default value for this string.
|
|
|
|
config INIT_ARM_PLL
|
|
bool "Initialize ARM PLL"
|
|
|
|
config INIT_SYS_PLL
|
|
bool "Initialize SYS PLL"
|
|
|
|
config INIT_USB1_PLL
|
|
bool "Initialize USB1 PLL"
|
|
|
|
config INIT_VIDEO_PLL
|
|
bool "Initialize Video PLL"
|
|
|
|
config ARM_DIV
|
|
int "ARM clock divider"
|
|
range 0 7
|
|
|
|
config AHB_DIV
|
|
int "AHB clock divider"
|
|
range 0 7
|
|
|
|
config IPG_DIV
|
|
int "IPG clock divider"
|
|
range 0 3
|
|
|
|
menuconfig NXP_IMX_RT_BOOT_HEADER
|
|
bool "Enable the boot header"
|
|
help
|
|
Enable data structures required by the boot ROM to boot the
|
|
application from an external flash device.
|
|
|
|
if NXP_IMX_RT_BOOT_HEADER
|
|
|
|
choice BOOT_DEVICE
|
|
prompt "Boot device selection"
|
|
default BOOT_FLEXSPI_NOR
|
|
|
|
config BOOT_FLEXSPI_NOR
|
|
bool "FlexSPI serial NOR"
|
|
|
|
config BOOT_FLEXSPI_NAND
|
|
bool "FlexSPI serial NAND"
|
|
|
|
config BOOT_SEMC_NOR
|
|
bool "SEMC parallel NOR"
|
|
|
|
config BOOT_SEMC_NAND
|
|
bool "SEMC parallel NAND"
|
|
|
|
endchoice
|
|
|
|
config IMAGE_VECTOR_TABLE_OFFSET
|
|
hex "Image vector table offset"
|
|
default 0x1000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR
|
|
default 0x400 if BOOT_FLEXSPI_NAND || BOOT_SEMC_NAND
|
|
help
|
|
The Image Vector Table (IVT) provides the boot ROM with pointers to
|
|
the application entry point and device configuration data. The boot
|
|
ROM requires a fixed IVT offset for each type of boot device.
|
|
|
|
config DEVICE_CONFIGURATION_DATA
|
|
bool "Enable device configuration data"
|
|
help
|
|
Device configuration data (DCD) provides a sequence of commands to
|
|
the boot ROM to initialize components such as an SDRAM.
|
|
|
|
endif # NXP_IMX_RT_BOOT_HEADER
|
|
|
|
choice CODE_LOCATION
|
|
prompt "Code location selection"
|
|
default CODE_ITCM
|
|
|
|
config CODE_ITCM
|
|
bool "Link code into internal instruction tightly coupled memory (ITCM)"
|
|
|
|
config CODE_FLEXSPI
|
|
bool "Link code into external FlexSPI-controlled memory"
|
|
select NXP_IMX_RT_BOOT_HEADER
|
|
|
|
config CODE_FLEXSPI2
|
|
bool "Link code into internal FlexSPI-controlled memory"
|
|
select NXP_IMX_RT_BOOT_HEADER
|
|
|
|
endchoice
|
|
|
|
choice DATA_LOCATION
|
|
prompt "Data location selection"
|
|
default DATA_DTCM
|
|
|
|
config DATA_DTCM
|
|
bool "Link data into internal data tightly coupled memory (DTCM)"
|
|
|
|
config DATA_SEMC
|
|
bool "Link data into external SEMC-controlled memory"
|
|
select DEVICE_CONFIGURATION_DATA if NXP_IMX_RT_BOOT_HEADER
|
|
|
|
config DATA_OCRAM
|
|
bool "Link data into On-Chip RAM memory"
|
|
|
|
endchoice
|
|
|
|
endif # SOC_SERIES_IMX_RT
|