61 lines
1.4 KiB
Plaintext
61 lines
1.4 KiB
Plaintext
/*
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* Copyright (c) 2019-2020 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Default Flash planning for nrf5340dk_nrf5340 CPUAPP (Application MCU).
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*
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* Zephyr build for nRF5340 with ARM TrustZone-M support,
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* implies building Secure and Non-Secure Zephyr images.
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*
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* Secure image will be placed, by default, in flash0
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* (or in slot0, if MCUboot is present).
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* Secure image will use sram0 for system memory.
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*
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* Non-Secure image will be placed in slot0_ns, and use
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* sram0_ns for system memory.
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*
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* Note that the Secure image only requires knowledge of
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* the beginning of the Non-Secure image (not its size).
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*/
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&slot0_partition {
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reg = <0x00010000 0x40000>;
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};
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&slot0_ns_partition {
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reg = <0x00050000 0x30000>;
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};
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&slot1_partition {
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reg = <0x00080000 0x40000>;
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};
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&slot1_ns_partition {
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reg = <0x000c0000 0x30000>;
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};
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/* Default SRAM planning when building for nRF5340 with
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* ARM TrustZone-M support
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* - Lowest 256 kB SRAM allocated to Secure image (sram0_s)
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* - Middle 192 kB allocated to Non-Secure image (sram0_ns)
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* - Upper 64 kB SRAM allocated as Shared memory (sram0_shared)
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* (see nrf5340_shared_sram_planning_conf.dtsi)
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*/
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&sram0_image {
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reg = <0x20000000 DT_SIZE_K(448)>;
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};
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&sram0_s {
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reg = <0x20000000 0x40000>;
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};
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&sram0_ns {
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reg = <0x20040000 0x30000>;
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};
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/* Include shared RAM configuration file */
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#include "nrf5340_shared_sram_planning_conf.dtsi"
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