20 lines
347 B
Plaintext
20 lines
347 B
Plaintext
/*
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* Copyright 2024 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* stm32F4 has a WWDG clock by APB1 where the APB1 prescaler is 1..16
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* this is too low to configure the WWDG clock for this sample.
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* Thus, use the IWDG instead for running this sample.
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*/
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&wwdg {
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status = "disabled";
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};
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&iwdg {
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status = "okay";
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};
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