909 lines
26 KiB
C
909 lines
26 KiB
C
/*
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*
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* Copyright (c) 2019 Linaro Limited.
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* Copyright (c) 2020 Jeremy LOCHE
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* Copyright (c) 2021 Electrolance Solutions
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_pwr.h>
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#include <stm32_ll_rcc.h>
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#include <stm32_ll_utils.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include "stm32_hsem.h"
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/* Macros to fill up prescaler values */
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#define z_hsi_divider(v) LL_RCC_HSI_DIV ## v
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#define hsi_divider(v) z_hsi_divider(v)
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#define z_sysclk_prescaler(v) LL_RCC_SYSCLK_DIV_ ## v
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#define sysclk_prescaler(v) z_sysclk_prescaler(v)
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#define z_ahb_prescaler(v) LL_RCC_AHB_DIV_ ## v
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#define ahb_prescaler(v) z_ahb_prescaler(v)
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#define z_apb1_prescaler(v) LL_RCC_APB1_DIV_ ## v
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#define apb1_prescaler(v) z_apb1_prescaler(v)
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#define z_apb2_prescaler(v) LL_RCC_APB2_DIV_ ## v
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#define apb2_prescaler(v) z_apb2_prescaler(v)
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#define z_apb3_prescaler(v) LL_RCC_APB3_DIV_ ## v
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#define apb3_prescaler(v) z_apb3_prescaler(v)
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#define z_apb4_prescaler(v) LL_RCC_APB4_DIV_ ## v
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#define apb4_prescaler(v) z_apb4_prescaler(v)
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/* Macro to check for clock feasibility */
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/* It is Cortex M7's responsibility to setup clock tree */
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/* This check should only be performed for the M7 core code */
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#ifdef CONFIG_CPU_CORTEX_M7
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/* Choose PLL SRC */
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#if defined(STM32_PLL_SRC_HSI)
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#define PLLSRC_FREQ ((STM32_HSI_FREQ)/(STM32_HSI_DIVISOR))
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#elif defined(STM32_PLL_SRC_CSI)
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#define PLLSRC_FREQ STM32_CSI_FREQ
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#elif defined(STM32_PLL_SRC_HSE)
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#define PLLSRC_FREQ STM32_HSE_FREQ
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#else
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#define PLLSRC_FREQ 0
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#endif
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/* Given source clock and dividers, computed the output frequency of PLLP */
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#define PLLP_FREQ(pllsrc_freq, divm, divn, divp) (((pllsrc_freq)*\
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(divn))/((divm)*(divp)))
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/* PLL P output frequency value */
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#define PLLP_VALUE PLLP_FREQ(\
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PLLSRC_FREQ,\
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STM32_PLL_M_DIVISOR,\
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STM32_PLL_N_MULTIPLIER,\
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STM32_PLL_P_DIVISOR)
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/* SYSCLKSRC before the D1CPRE prescaler */
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#if defined(STM32_SYSCLK_SRC_PLL)
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#define SYSCLKSRC_FREQ PLLP_VALUE
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#elif defined(STM32_SYSCLK_SRC_HSI)
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#define SYSCLKSRC_FREQ ((STM32_HSI_FREQ)/(STM32_HSI_DIVISOR))
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#elif defined(STM32_SYSCLK_SRC_CSI)
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#define SYSCLKSRC_FREQ STM32_CSI_FREQ
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#elif defined(STM32_SYSCLK_SRC_HSE)
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#define SYSCLKSRC_FREQ STM32_HSE_FREQ
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#endif
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/* ARM Sys CPU Clock before HPRE prescaler */
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#define SYSCLK_FREQ ((SYSCLKSRC_FREQ)/(STM32_D1CPRE))
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#define AHB_FREQ ((SYSCLK_FREQ)/(STM32_HPRE))
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#define APB1_FREQ ((AHB_FREQ)/(STM32_D2PPRE1))
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#define APB2_FREQ ((AHB_FREQ)/(STM32_D2PPRE2))
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#define APB3_FREQ ((AHB_FREQ)/(STM32_D1PPRE))
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#define APB4_FREQ ((AHB_FREQ)/(STM32_D3PPRE))
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/* Datasheet maximum frequency definitions */
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#if defined(CONFIG_SOC_STM32H743XX) ||\
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defined(CONFIG_SOC_STM32H745XX) ||\
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defined(CONFIG_SOC_STM32H747XX) ||\
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defined(CONFIG_SOC_STM32H750XX) ||\
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defined(CONFIG_SOC_STM32H753XX)
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/* All h7 SoC with maximum 480MHz SYSCLK */
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#define SYSCLK_FREQ_MAX 480000000UL
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#define AHB_FREQ_MAX 240000000UL
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#define APBx_FREQ_MAX 120000000UL
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#elif defined(CONFIG_SOC_STM32H723XX) ||\
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defined(CONFIG_SOC_STM32H725XX) ||\
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defined(CONFIG_SOC_STM32H730XX) ||\
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defined(CONFIG_SOC_STM32H735XX)
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/* All h7 SoC with maximum 550MHz SYSCLK */
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#define SYSCLK_FREQ_MAX 550000000UL
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#define AHB_FREQ_MAX 275000000UL
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#define APBx_FREQ_MAX 137500000UL
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#elif defined(CONFIG_SOC_STM32H7A3XX) || defined(CONFIG_SOC_STM32H7A3XXQ) ||\
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defined(CONFIG_SOC_STM32H7B3XX) || defined(CONFIG_SOC_STM32H7B3XXQ)
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#define SYSCLK_FREQ_MAX 280000000UL
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#define AHB_FREQ_MAX 280000000UL
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#define APBx_FREQ_MAX 140000000UL
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#else
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/* Default: All h7 SoC with maximum 280MHz SYSCLK */
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#define SYSCLK_FREQ_MAX 280000000UL
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#define AHB_FREQ_MAX 140000000UL
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#define APBx_FREQ_MAX 70000000UL
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#endif
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#if SYSCLK_FREQ > SYSCLK_FREQ_MAX
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#error "SYSCLK frequency is too high!"
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#endif
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#if AHB_FREQ > AHB_FREQ_MAX
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#error "AHB frequency is too high!"
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#endif
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#if APB1_FREQ > APBx_FREQ_MAX
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#error "APB1 frequency is too high!"
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#endif
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#if APB2_FREQ > APBx_FREQ_MAX
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#error "APB2 frequency is too high!"
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#endif
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#if APB3_FREQ > APBx_FREQ_MAX
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#error "APB3 frequency is too high!"
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#endif
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#if APB4_FREQ > APBx_FREQ_MAX
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#error "APB4 frequency is too high!"
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#endif
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#if SYSCLK_FREQ != CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
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#error "SYS clock frequency for M7 core doesn't match CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC"
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#endif
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/* end of clock feasability check */
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#endif /* CONFIG_CPU_CORTEX_M7 */
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#if defined(CONFIG_CPU_CORTEX_M7)
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#if STM32_D1CPRE > 1
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/*
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* D1CPRE prescaler allows to set a HCLK frequency lower than SYSCLK frequency.
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* Though, zephyr doesn't make a difference today between these two clocks.
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* So, changing this prescaler is not allowed until it is made possible to
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* use them independently in zephyr clock subsystem.
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*/
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#error "D1CPRE presacler can't be higher than 1"
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#endif
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#endif /* CONFIG_CPU_CORTEX_M7 */
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#if defined(CONFIG_CPU_CORTEX_M7)
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/* Offset to access bus clock registers from M7 (or only) core */
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#define STM32H7_BUS_CLK_REG DT_REG_ADDR(DT_NODELABEL(rcc))
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#elif defined(CONFIG_CPU_CORTEX_M4)
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/* Offset to access bus clock registers from M4 core */
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#define STM32H7_BUS_CLK_REG DT_REG_ADDR(DT_NODELABEL(rcc)) + 0x60
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#endif
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static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler)
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{
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return clock / prescaler;
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}
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__unused
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static uint32_t get_pllout_frequency(uint32_t pllsrc_freq,
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int pllm_div,
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int plln_mul,
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int pllout_div)
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{
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__ASSERT_NO_MSG(pllm_div && pllout_div);
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return (pllsrc_freq / pllm_div) * plln_mul / pllout_div;
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}
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__unused
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static uint32_t get_pllsrc_frequency(void)
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{
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switch (LL_RCC_PLL_GetSource()) {
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case LL_RCC_PLLSOURCE_HSI:
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return STM32_HSI_FREQ;
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case LL_RCC_PLLSOURCE_CSI:
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return STM32_CSI_FREQ;
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case LL_RCC_PLLSOURCE_HSE:
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return STM32_HSE_FREQ;
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case LL_RCC_PLLSOURCE_NONE:
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default:
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return 0;
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}
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}
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__unused
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static uint32_t get_hclk_frequency(void)
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{
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uint32_t sysclk = 0;
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/* Get the current system clock source */
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switch (LL_RCC_GetSysClkSource()) {
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case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:
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sysclk = STM32_HSI_FREQ/STM32_HSI_DIVISOR;
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break;
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case LL_RCC_SYS_CLKSOURCE_STATUS_CSI:
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sysclk = STM32_CSI_FREQ;
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break;
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case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:
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sysclk = STM32_HSE_FREQ;
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break;
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#if defined(STM32_PLL_ENABLED)
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case LL_RCC_SYS_CLKSOURCE_STATUS_PLL1:
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sysclk = get_pllout_frequency(get_pllsrc_frequency(),
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STM32_PLL_M_DIVISOR,
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STM32_PLL_N_MULTIPLIER,
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STM32_PLL_P_DIVISOR);
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break;
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#endif /* STM32_PLL_ENABLED */
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}
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return get_bus_clock(sysclk, STM32_HPRE);
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}
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#if !defined(CONFIG_CPU_CORTEX_M4)
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static int32_t prepare_regulator_voltage_scale(void)
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{
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/* Apply system power supply configuration */
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#if defined(SMPS) && defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS)
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LL_PWR_ConfigSupply(LL_PWR_DIRECT_SMPS_SUPPLY);
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#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO)
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LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_LDO);
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#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_LDO)
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LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_LDO);
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#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO)
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LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO);
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#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT_AND_LDO)
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LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO);
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#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT)
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LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT);
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#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT)
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LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT);
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#elif defined(CONFIG_POWER_SUPPLY_EXTERNAL_SOURCE)
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LL_PWR_ConfigSupply(LL_PWR_EXTERNAL_SOURCE_SUPPLY);
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#else
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LL_PWR_ConfigSupply(LL_PWR_LDO_SUPPLY);
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#endif
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/* Make sure to put the CPU in highest Voltage scale during clock configuration */
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/* Highest voltage is SCALE0 */
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LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE0);
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while (LL_PWR_IsActiveFlag_VOS() == 0) {
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}
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return 0;
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}
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static int32_t optimize_regulator_voltage_scale(uint32_t sysclk_freq)
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{
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/* After sysclock is configured, tweak the voltage scale down */
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/* to reduce power consumption */
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/* Needs some smart work to configure properly */
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/* LL_PWR_REGULATOR_SCALE3 is lowest power consumption */
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/* Must be done in accordance to the Maximum allowed frequency vs VOS*/
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/* See RM0433 page 352 for more details */
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#if defined(SMPS) && defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS)
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LL_PWR_ConfigSupply(LL_PWR_DIRECT_SMPS_SUPPLY);
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#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO)
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LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_LDO);
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#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_LDO)
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LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_LDO);
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#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO)
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LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO);
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#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT_AND_LDO)
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LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO);
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#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT)
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LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT);
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#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT)
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LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT);
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#elif defined(CONFIG_POWER_SUPPLY_EXTERNAL_SOURCE)
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LL_PWR_ConfigSupply(LL_PWR_EXTERNAL_SOURCE_SUPPLY);
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#else
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LL_PWR_ConfigSupply(LL_PWR_LDO_SUPPLY);
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#endif
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LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE0);
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while (LL_PWR_IsActiveFlag_VOS() == 0) {
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}
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return 0;
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}
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__unused
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static int get_vco_input_range(uint32_t m_div, uint32_t *range)
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{
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uint32_t vco_freq;
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vco_freq = PLLSRC_FREQ / m_div;
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if (MHZ(1) <= vco_freq && vco_freq <= MHZ(2)) {
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*range = LL_RCC_PLLINPUTRANGE_1_2;
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} else if (MHZ(2) < vco_freq && vco_freq <= MHZ(4)) {
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*range = LL_RCC_PLLINPUTRANGE_2_4;
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} else if (MHZ(4) < vco_freq && vco_freq <= MHZ(8)) {
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*range = LL_RCC_PLLINPUTRANGE_4_8;
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} else if (MHZ(8) < vco_freq && vco_freq <= MHZ(16)) {
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*range = LL_RCC_PLLINPUTRANGE_8_16;
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} else {
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return -ERANGE;
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}
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return 0;
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}
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__unused
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static uint32_t get_vco_output_range(uint32_t vco_input_range)
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{
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if (vco_input_range == LL_RCC_PLLINPUTRANGE_1_2) {
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return LL_RCC_PLLVCORANGE_MEDIUM;
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}
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return LL_RCC_PLLVCORANGE_WIDE;
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}
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#endif /* ! CONFIG_CPU_CORTEX_M4 */
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/** @brief Verifies clock is part of actve clock configuration */
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static int enabled_clock(uint32_t src_clk)
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{
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if ((src_clk == STM32_SRC_SYSCLK) ||
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((src_clk == STM32_SRC_CKPER) && IS_ENABLED(STM32_CKPER_ENABLED)) ||
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((src_clk == STM32_SRC_HSE) && IS_ENABLED(STM32_HSE_ENABLED)) ||
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((src_clk == STM32_SRC_HSI_KER) && IS_ENABLED(STM32_HSI_ENABLED)) ||
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((src_clk == STM32_SRC_CSI_KER) && IS_ENABLED(STM32_CSI_ENABLED)) ||
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((src_clk == STM32_SRC_LSE) && IS_ENABLED(STM32_LSE_ENABLED)) ||
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((src_clk == STM32_SRC_LSI) && IS_ENABLED(STM32_LSI_ENABLED)) ||
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((src_clk == STM32_SRC_PLL1_P) && IS_ENABLED(STM32_PLL_P_ENABLED)) ||
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((src_clk == STM32_SRC_PLL1_Q) && IS_ENABLED(STM32_PLL_Q_ENABLED)) ||
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((src_clk == STM32_SRC_PLL1_R) && IS_ENABLED(STM32_PLL_R_ENABLED)) ||
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((src_clk == STM32_SRC_PLL2_P) && IS_ENABLED(STM32_PLL2_P_ENABLED)) ||
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((src_clk == STM32_SRC_PLL2_Q) && IS_ENABLED(STM32_PLL2_Q_ENABLED)) ||
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((src_clk == STM32_SRC_PLL2_R) && IS_ENABLED(STM32_PLL2_R_ENABLED)) ||
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((src_clk == STM32_SRC_PLL3_P) && IS_ENABLED(STM32_PLL3_P_ENABLED)) ||
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((src_clk == STM32_SRC_PLL3_Q) && IS_ENABLED(STM32_PLL3_Q_ENABLED)) ||
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((src_clk == STM32_SRC_PLL3_R) && IS_ENABLED(STM32_PLL3_R_ENABLED))) {
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return 0;
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}
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return -ENOTSUP;
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}
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static inline int stm32_clock_control_on(const struct device *dev,
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clock_control_subsys_t sub_system)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
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volatile uint32_t *reg;
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uint32_t reg_val;
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ARG_UNUSED(dev);
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if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
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/* Attemp to toggle a wrong periph clock bit */
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return -ENOTSUP;
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}
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z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
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reg = (uint32_t *)(STM32H7_BUS_CLK_REG + pclken->bus);
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reg_val = *reg;
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reg_val |= pclken->enr;
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*reg = reg_val;
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z_stm32_hsem_unlock(CFG_HW_RCC_SEMID);
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return 0;
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}
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static inline int stm32_clock_control_off(const struct device *dev,
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clock_control_subsys_t sub_system)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
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volatile uint32_t *reg;
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uint32_t reg_val;
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ARG_UNUSED(dev);
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if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
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/* Attemp to toggle a wrong periph clock bit */
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return -ENOTSUP;
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}
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z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
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reg = (uint32_t *)(STM32H7_BUS_CLK_REG + pclken->bus);
|
|
reg_val = *reg;
|
|
reg_val &= ~pclken->enr;
|
|
*reg = reg_val;
|
|
|
|
z_stm32_hsem_unlock(CFG_HW_RCC_SEMID);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static inline int stm32_clock_control_configure(const struct device *dev,
|
|
clock_control_subsys_t sub_system,
|
|
void *data)
|
|
{
|
|
struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
|
|
volatile uint32_t *reg;
|
|
uint32_t reg_val, dt_val;
|
|
int err;
|
|
|
|
ARG_UNUSED(dev);
|
|
ARG_UNUSED(data);
|
|
|
|
err = enabled_clock(pclken->bus);
|
|
if (err < 0) {
|
|
/* Attemp to configure a src clock not available or not valid */
|
|
return err;
|
|
}
|
|
|
|
z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
|
|
|
|
dt_val = STM32_CLOCK_VAL_GET(pclken->enr) <<
|
|
STM32_CLOCK_SHIFT_GET(pclken->enr);
|
|
reg = (uint32_t *)(DT_REG_ADDR(DT_NODELABEL(rcc)) +
|
|
STM32_CLOCK_REG_GET(pclken->enr));
|
|
reg_val = *reg;
|
|
reg_val &= ~dt_val;
|
|
reg_val |= dt_val;
|
|
*reg = reg_val;
|
|
|
|
z_stm32_hsem_unlock(CFG_HW_RCC_SEMID);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_clock_control_get_subsys_rate(const struct device *clock,
|
|
clock_control_subsys_t sub_system,
|
|
uint32_t *rate)
|
|
{
|
|
struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
|
|
/*
|
|
* Get AHB Clock (= SystemCoreClock = SYSCLK/prescaler)
|
|
* SystemCoreClock is preferred to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
|
|
* since it will be updated after clock configuration and hence
|
|
* more likely to contain actual clock speed
|
|
*/
|
|
#if defined(CONFIG_CPU_CORTEX_M4)
|
|
uint32_t ahb_clock = SystemCoreClock;
|
|
#else
|
|
uint32_t ahb_clock = get_bus_clock(SystemCoreClock, STM32_HPRE);
|
|
#endif
|
|
uint32_t apb1_clock = get_bus_clock(ahb_clock, STM32_D2PPRE1);
|
|
uint32_t apb2_clock = get_bus_clock(ahb_clock, STM32_D2PPRE2);
|
|
uint32_t apb3_clock = get_bus_clock(ahb_clock, STM32_D1PPRE);
|
|
uint32_t apb4_clock = get_bus_clock(ahb_clock, STM32_D3PPRE);
|
|
|
|
ARG_UNUSED(clock);
|
|
|
|
switch (pclken->bus) {
|
|
case STM32_CLOCK_BUS_AHB1:
|
|
case STM32_CLOCK_BUS_AHB2:
|
|
case STM32_CLOCK_BUS_AHB3:
|
|
case STM32_CLOCK_BUS_AHB4:
|
|
*rate = ahb_clock;
|
|
break;
|
|
case STM32_CLOCK_BUS_APB1:
|
|
case STM32_CLOCK_BUS_APB1_2:
|
|
*rate = apb1_clock;
|
|
break;
|
|
case STM32_CLOCK_BUS_APB2:
|
|
*rate = apb2_clock;
|
|
break;
|
|
case STM32_CLOCK_BUS_APB3:
|
|
*rate = apb3_clock;
|
|
break;
|
|
case STM32_CLOCK_BUS_APB4:
|
|
*rate = apb4_clock;
|
|
break;
|
|
case STM32_SRC_SYSCLK:
|
|
*rate = get_hclk_frequency();
|
|
break;
|
|
#if defined(STM32_CKPER_ENABLED)
|
|
case STM32_SRC_CKPER:
|
|
*rate = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
|
|
break;
|
|
#endif /* STM32_CKPER_ENABLED */
|
|
#if defined(STM32_HSE_ENABLED)
|
|
case STM32_SRC_HSE:
|
|
*rate = STM32_HSE_FREQ;
|
|
break;
|
|
#endif /* STM32_HSE_ENABLED */
|
|
#if defined(STM32_LSE_ENABLED)
|
|
case STM32_SRC_LSE:
|
|
*rate = STM32_LSE_FREQ;
|
|
break;
|
|
#endif /* STM32_LSE_ENABLED */
|
|
#if defined(STM32_LSI_ENABLED)
|
|
case STM32_SRC_LSI:
|
|
*rate = STM32_LSI_FREQ;
|
|
break;
|
|
#endif /* STM32_LSI_ENABLED */
|
|
#if defined(STM32_PLL_ENABLED)
|
|
case STM32_SRC_PLL1_P:
|
|
*rate = get_pllout_frequency(get_pllsrc_frequency(),
|
|
STM32_PLL_M_DIVISOR,
|
|
STM32_PLL_N_MULTIPLIER,
|
|
STM32_PLL_P_DIVISOR);
|
|
break;
|
|
case STM32_SRC_PLL1_Q:
|
|
*rate = get_pllout_frequency(get_pllsrc_frequency(),
|
|
STM32_PLL_M_DIVISOR,
|
|
STM32_PLL_N_MULTIPLIER,
|
|
STM32_PLL_Q_DIVISOR);
|
|
break;
|
|
case STM32_SRC_PLL1_R:
|
|
*rate = get_pllout_frequency(get_pllsrc_frequency(),
|
|
STM32_PLL_M_DIVISOR,
|
|
STM32_PLL_N_MULTIPLIER,
|
|
STM32_PLL_R_DIVISOR);
|
|
break;
|
|
#endif /* STM32_PLL_ENABLED */
|
|
#if defined(STM32_PLL2_ENABLED)
|
|
case STM32_SRC_PLL2_P:
|
|
*rate = get_pllout_frequency(get_pllsrc_frequency(),
|
|
STM32_PLL2_M_DIVISOR,
|
|
STM32_PLL2_N_MULTIPLIER,
|
|
STM32_PLL2_P_DIVISOR);
|
|
break;
|
|
case STM32_SRC_PLL2_Q:
|
|
*rate = get_pllout_frequency(get_pllsrc_frequency(),
|
|
STM32_PLL2_M_DIVISOR,
|
|
STM32_PLL2_N_MULTIPLIER,
|
|
STM32_PLL2_Q_DIVISOR);
|
|
break;
|
|
case STM32_SRC_PLL2_R:
|
|
*rate = get_pllout_frequency(get_pllsrc_frequency(),
|
|
STM32_PLL2_M_DIVISOR,
|
|
STM32_PLL2_N_MULTIPLIER,
|
|
STM32_PLL2_R_DIVISOR);
|
|
break;
|
|
#endif /* STM32_PLL2_ENABLED */
|
|
#if defined(STM32_PLL3_ENABLED)
|
|
case STM32_SRC_PLL3_P:
|
|
*rate = get_pllout_frequency(get_pllsrc_frequency(),
|
|
STM32_PLL3_M_DIVISOR,
|
|
STM32_PLL3_N_MULTIPLIER,
|
|
STM32_PLL3_P_DIVISOR);
|
|
break;
|
|
case STM32_SRC_PLL3_Q:
|
|
*rate = get_pllout_frequency(get_pllsrc_frequency(),
|
|
STM32_PLL3_M_DIVISOR,
|
|
STM32_PLL3_N_MULTIPLIER,
|
|
STM32_PLL3_Q_DIVISOR);
|
|
break;
|
|
case STM32_SRC_PLL3_R:
|
|
*rate = get_pllout_frequency(get_pllsrc_frequency(),
|
|
STM32_PLL3_M_DIVISOR,
|
|
STM32_PLL3_N_MULTIPLIER,
|
|
STM32_PLL3_R_DIVISOR);
|
|
break;
|
|
#endif /* STM32_PLL3_ENABLED */
|
|
default:
|
|
return -ENOTSUP;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct clock_control_driver_api stm32_clock_control_api = {
|
|
.on = stm32_clock_control_on,
|
|
.off = stm32_clock_control_off,
|
|
.get_rate = stm32_clock_control_get_subsys_rate,
|
|
.configure = stm32_clock_control_configure,
|
|
};
|
|
|
|
__unused
|
|
static void set_up_fixed_clock_sources(void)
|
|
{
|
|
|
|
if (IS_ENABLED(STM32_HSE_ENABLED)) {
|
|
/* Enable HSE oscillator */
|
|
if (IS_ENABLED(STM32_HSE_BYPASS)) {
|
|
LL_RCC_HSE_EnableBypass();
|
|
} else {
|
|
LL_RCC_HSE_DisableBypass();
|
|
}
|
|
|
|
LL_RCC_HSE_Enable();
|
|
while (LL_RCC_HSE_IsReady() != 1) {
|
|
}
|
|
}
|
|
|
|
if (IS_ENABLED(STM32_HSI_ENABLED)) {
|
|
/* Enable HSI oscillator */
|
|
LL_RCC_HSI_Enable();
|
|
while (LL_RCC_HSI_IsReady() != 1) {
|
|
}
|
|
/* HSI divider configuration */
|
|
LL_RCC_HSI_SetDivider(hsi_divider(STM32_HSI_DIVISOR));
|
|
}
|
|
|
|
if (IS_ENABLED(STM32_CSI_ENABLED)) {
|
|
/* Enable CSI oscillator */
|
|
LL_RCC_CSI_Enable();
|
|
while (LL_RCC_CSI_IsReady() != 1) {
|
|
}
|
|
}
|
|
|
|
if (IS_ENABLED(STM32_LSI_ENABLED)) {
|
|
/* Enable LSI oscillator */
|
|
LL_RCC_LSI_Enable();
|
|
while (LL_RCC_LSI_IsReady() != 1) {
|
|
}
|
|
}
|
|
|
|
if (IS_ENABLED(STM32_LSE_ENABLED)) {
|
|
/* Enable backup domain */
|
|
LL_PWR_EnableBkUpAccess();
|
|
|
|
/* Configure driving capability */
|
|
LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR_LSEDRV_Pos);
|
|
|
|
if (IS_ENABLED(STM32_LSE_BYPASS)) {
|
|
/* Configure LSE bypass */
|
|
LL_RCC_LSE_EnableBypass();
|
|
}
|
|
|
|
/* Enable LSE oscillator */
|
|
LL_RCC_LSE_Enable();
|
|
while (LL_RCC_LSE_IsReady() != 1) {
|
|
}
|
|
}
|
|
}
|
|
|
|
__unused
|
|
static int set_up_plls(void)
|
|
{
|
|
#if defined(STM32_PLL_ENABLED) || defined(STM32_PLL2_ENABLED) || defined(STM32_PLL3_ENABLED)
|
|
int r;
|
|
uint32_t vco_input_range;
|
|
uint32_t vco_output_range;
|
|
|
|
/* Configure PLL source */
|
|
|
|
/* Can be HSE , HSI 64Mhz/HSIDIV, CSI 4MHz*/
|
|
if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
|
|
/* Main PLL configuration and activation */
|
|
LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSE);
|
|
} else if (IS_ENABLED(STM32_PLL_SRC_CSI)) {
|
|
/* Main PLL configuration and activation */
|
|
LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_CSI);
|
|
} else if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
|
|
/* Main PLL configuration and activation */
|
|
LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSI);
|
|
} else {
|
|
return -ENOTSUP;
|
|
}
|
|
|
|
#if defined(STM32_PLL_ENABLED)
|
|
r = get_vco_input_range(STM32_PLL_M_DIVISOR, &vco_input_range);
|
|
if (r < 0) {
|
|
return r;
|
|
}
|
|
|
|
vco_output_range = get_vco_output_range(vco_input_range);
|
|
|
|
LL_RCC_PLL1_SetM(STM32_PLL_M_DIVISOR);
|
|
|
|
LL_RCC_PLL1_SetVCOInputRange(vco_input_range);
|
|
LL_RCC_PLL1_SetVCOOutputRange(vco_output_range);
|
|
|
|
LL_RCC_PLL1_SetN(STM32_PLL_N_MULTIPLIER);
|
|
|
|
/* FRACN disable DIVP,DIVQ,DIVR enable*/
|
|
LL_RCC_PLL1FRACN_Disable();
|
|
|
|
if (IS_ENABLED(STM32_PLL_P_ENABLED)) {
|
|
LL_RCC_PLL1_SetP(STM32_PLL_P_DIVISOR);
|
|
LL_RCC_PLL1P_Enable();
|
|
}
|
|
|
|
if (IS_ENABLED(STM32_PLL_Q_ENABLED)) {
|
|
LL_RCC_PLL1_SetQ(STM32_PLL_Q_DIVISOR);
|
|
LL_RCC_PLL1Q_Enable();
|
|
}
|
|
|
|
if (IS_ENABLED(STM32_PLL_R_ENABLED)) {
|
|
LL_RCC_PLL1_SetR(STM32_PLL_R_DIVISOR);
|
|
LL_RCC_PLL1R_Enable();
|
|
}
|
|
|
|
LL_RCC_PLL1_Enable();
|
|
while (LL_RCC_PLL1_IsReady() != 1U) {
|
|
}
|
|
|
|
#endif /* STM32_PLL_ENABLED */
|
|
|
|
#if defined(STM32_PLL2_ENABLED)
|
|
r = get_vco_input_range(STM32_PLL2_M_DIVISOR, &vco_input_range);
|
|
if (r < 0) {
|
|
return r;
|
|
}
|
|
|
|
vco_output_range = get_vco_output_range(vco_input_range);
|
|
|
|
LL_RCC_PLL2_SetM(STM32_PLL2_M_DIVISOR);
|
|
|
|
LL_RCC_PLL2_SetVCOInputRange(vco_input_range);
|
|
LL_RCC_PLL2_SetVCOOutputRange(vco_output_range);
|
|
|
|
LL_RCC_PLL2_SetN(STM32_PLL2_N_MULTIPLIER);
|
|
|
|
LL_RCC_PLL2FRACN_Disable();
|
|
|
|
if (IS_ENABLED(STM32_PLL2_P_ENABLED)) {
|
|
LL_RCC_PLL2_SetP(STM32_PLL2_P_DIVISOR);
|
|
LL_RCC_PLL2P_Enable();
|
|
}
|
|
|
|
if (IS_ENABLED(STM32_PLL2_Q_ENABLED)) {
|
|
LL_RCC_PLL2_SetQ(STM32_PLL2_Q_DIVISOR);
|
|
LL_RCC_PLL2Q_Enable();
|
|
}
|
|
|
|
if (IS_ENABLED(STM32_PLL2_R_ENABLED)) {
|
|
LL_RCC_PLL2_SetR(STM32_PLL2_R_DIVISOR);
|
|
LL_RCC_PLL2R_Enable();
|
|
}
|
|
|
|
LL_RCC_PLL2_Enable();
|
|
while (LL_RCC_PLL2_IsReady() != 1U) {
|
|
}
|
|
|
|
#endif /* STM32_PLL2_ENABLED */
|
|
|
|
#if defined(STM32_PLL3_ENABLED)
|
|
r = get_vco_input_range(STM32_PLL3_M_DIVISOR, &vco_input_range);
|
|
if (r < 0) {
|
|
return r;
|
|
}
|
|
|
|
vco_output_range = get_vco_output_range(vco_input_range);
|
|
|
|
LL_RCC_PLL3_SetM(STM32_PLL3_M_DIVISOR);
|
|
|
|
LL_RCC_PLL3_SetVCOInputRange(vco_input_range);
|
|
LL_RCC_PLL3_SetVCOOutputRange(vco_output_range);
|
|
|
|
LL_RCC_PLL3_SetN(STM32_PLL3_N_MULTIPLIER);
|
|
|
|
LL_RCC_PLL3FRACN_Disable();
|
|
|
|
if (IS_ENABLED(STM32_PLL3_P_ENABLED)) {
|
|
LL_RCC_PLL3_SetP(STM32_PLL3_P_DIVISOR);
|
|
LL_RCC_PLL3P_Enable();
|
|
}
|
|
|
|
if (IS_ENABLED(STM32_PLL3_Q_ENABLED)) {
|
|
LL_RCC_PLL3_SetQ(STM32_PLL3_Q_DIVISOR);
|
|
LL_RCC_PLL3Q_Enable();
|
|
}
|
|
|
|
if (IS_ENABLED(STM32_PLL3_R_ENABLED)) {
|
|
LL_RCC_PLL3_SetR(STM32_PLL3_R_DIVISOR);
|
|
LL_RCC_PLL3R_Enable();
|
|
}
|
|
|
|
LL_RCC_PLL3_Enable();
|
|
while (LL_RCC_PLL3_IsReady() != 1U) {
|
|
}
|
|
|
|
#endif /* STM32_PLL3_ENABLED */
|
|
|
|
#else
|
|
/* Init PLL source to None */
|
|
LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_NONE);
|
|
|
|
#endif /* STM32_PLL_ENABLED || STM32_PLL2_ENABLED || STM32_PLL3_ENABLED */
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if defined(CONFIG_CPU_CORTEX_M7)
|
|
static int stm32_clock_control_init(const struct device *dev)
|
|
{
|
|
uint32_t old_hclk_freq = 0;
|
|
uint32_t new_hclk_freq = 0;
|
|
int r;
|
|
|
|
ARG_UNUSED(dev);
|
|
|
|
/* HW semaphore Clock enable */
|
|
#if defined(CONFIG_SOC_STM32H7A3XX) || defined(CONFIG_SOC_STM32H7A3XXQ) || \
|
|
defined(CONFIG_SOC_STM32H7B3XX) || defined(CONFIG_SOC_STM32H7B3XXQ)
|
|
LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_HSEM);
|
|
#else
|
|
LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_HSEM);
|
|
#endif
|
|
|
|
z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
|
|
|
|
/* Set up indiviual enabled clocks */
|
|
set_up_fixed_clock_sources();
|
|
|
|
/* Set up PLLs */
|
|
r = set_up_plls();
|
|
if (r < 0) {
|
|
return r;
|
|
}
|
|
|
|
/* Configure Voltage scale to comply with the desired system frequency */
|
|
prepare_regulator_voltage_scale();
|
|
|
|
/* Current hclk value */
|
|
old_hclk_freq = get_hclk_frequency();
|
|
/* AHB is HCLK clock to configure */
|
|
new_hclk_freq = get_bus_clock(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
|
|
STM32_HPRE);
|
|
|
|
/* Set flash latency */
|
|
/* AHB/AXI/HCLK clock is SYSCLK / HPRE */
|
|
/* If freq increases, set flash latency before any clock setting */
|
|
if (new_hclk_freq > old_hclk_freq) {
|
|
LL_SetFlashLatency(new_hclk_freq);
|
|
}
|
|
|
|
/* Preset the prescalers prior to chosing SYSCLK */
|
|
/* Prevents APB clock to go over limits */
|
|
/* Set buses (Sys,AHB, APB1, APB2 & APB4) prescalers */
|
|
LL_RCC_SetSysPrescaler(sysclk_prescaler(STM32_D1CPRE));
|
|
LL_RCC_SetAHBPrescaler(ahb_prescaler(STM32_HPRE));
|
|
LL_RCC_SetAPB1Prescaler(apb1_prescaler(STM32_D2PPRE1));
|
|
LL_RCC_SetAPB2Prescaler(apb2_prescaler(STM32_D2PPRE2));
|
|
LL_RCC_SetAPB3Prescaler(apb3_prescaler(STM32_D1PPRE));
|
|
LL_RCC_SetAPB4Prescaler(apb4_prescaler(STM32_D3PPRE));
|
|
|
|
/* Set up sys clock */
|
|
if (IS_ENABLED(STM32_SYSCLK_SRC_PLL)) {
|
|
/* Set PLL1 as System Clock Source */
|
|
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
|
|
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1) {
|
|
}
|
|
} else if (IS_ENABLED(STM32_SYSCLK_SRC_HSE)) {
|
|
/* Set sysclk source to HSE */
|
|
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
|
|
while (LL_RCC_GetSysClkSource() !=
|
|
LL_RCC_SYS_CLKSOURCE_STATUS_HSE) {
|
|
}
|
|
} else if (IS_ENABLED(STM32_SYSCLK_SRC_HSI)) {
|
|
/* Set sysclk source to HSI */
|
|
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
|
|
while (LL_RCC_GetSysClkSource() !=
|
|
LL_RCC_SYS_CLKSOURCE_STATUS_HSI) {
|
|
}
|
|
} else if (IS_ENABLED(STM32_SYSCLK_SRC_CSI)) {
|
|
/* Set sysclk source to CSI */
|
|
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_CSI);
|
|
while (LL_RCC_GetSysClkSource() !=
|
|
LL_RCC_SYS_CLKSOURCE_STATUS_CSI) {
|
|
}
|
|
} else {
|
|
return -ENOTSUP;
|
|
}
|
|
|
|
/* Set FLASH latency */
|
|
/* AHB/AXI/HCLK clock is SYSCLK / HPRE */
|
|
/* If freq not increased, set flash latency after all clock setting */
|
|
if (new_hclk_freq <= old_hclk_freq) {
|
|
LL_SetFlashLatency(new_hclk_freq);
|
|
}
|
|
|
|
optimize_regulator_voltage_scale(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
|
|
|
|
z_stm32_hsem_unlock(CFG_HW_RCC_SEMID);
|
|
|
|
/* Update CMSIS variable */
|
|
SystemCoreClock = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
|
|
|
|
return r;
|
|
}
|
|
#else
|
|
static int stm32_clock_control_init(const struct device *dev)
|
|
{
|
|
ARG_UNUSED(dev);
|
|
|
|
/* Update CMSIS variable */
|
|
SystemCoreClock = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
|
|
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_CPU_CORTEX_M7 */
|
|
|
|
/**
|
|
* @brief RCC device, note that priority is intentionally set to 1 so
|
|
* that the device init runs just after SOC init
|
|
*/
|
|
DEVICE_DT_DEFINE(DT_NODELABEL(rcc),
|
|
&stm32_clock_control_init,
|
|
NULL,
|
|
NULL, NULL,
|
|
PRE_KERNEL_1,
|
|
CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
|
|
&stm32_clock_control_api);
|