90 lines
1.9 KiB
C
90 lines
1.9 KiB
C
/* pinmux_dev_qmsi.c - QMSI pinmux dev driver */
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/*
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* Copyright (c) 2016 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <pinmux.h>
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#include "qm_pinmux.h"
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#define MASK_2_BITS 0x3
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static int pinmux_dev_set(struct device *dev, uint32_t pin,
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uint32_t func)
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{
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ARG_UNUSED(dev);
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return qm_pmux_select(pin, func) == 0 ? 0 : -EIO;
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}
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static int pinmux_dev_get(struct device *dev, uint32_t pin,
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uint32_t *func)
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{
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ARG_UNUSED(dev);
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/*
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* pinmux control registers are 32-bit wide, but each pin requires
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* 2 bits to set the mode (A, B, C, or D). As such we only get 16
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* pins per register.
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*/
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uint32_t reg_offset = pin >> 4;
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/* The pin offset within the register */
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uint32_t pin_no = pin % 16;
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/*
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* Now figure out what is the full address for the register
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* we are looking for.
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*/
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volatile uint32_t *mux_register = &QM_SCSS_PMUX->pmux_sel[reg_offset];
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/*
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* MASK_2_BITS (the value of which is 3) is used because there are
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* 2 bits for the mode of each pin.
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*/
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uint32_t pin_mask = MASK_2_BITS << (pin_no << 1);
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uint32_t mode_mask = *mux_register & pin_mask;
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uint32_t mode = mode_mask >> (pin_no << 1);
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*func = mode;
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return 0;
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}
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static int pinmux_dev_pullup(struct device *dev, uint32_t pin,
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uint8_t func)
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{
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ARG_UNUSED(dev);
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return qm_pmux_pullup_en(pin, func) == 0 ? 0 : -EIO;
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}
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static int pinmux_dev_input(struct device *dev, uint32_t pin,
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uint8_t func)
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{
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ARG_UNUSED(dev);
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return qm_pmux_input_en(pin, func) == 0 ? 0 : -EIO;
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}
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static struct pinmux_driver_api api_funcs = {
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.set = pinmux_dev_set,
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.get = pinmux_dev_get,
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.pullup = pinmux_dev_pullup,
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.input = pinmux_dev_input
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};
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static int pinmux_dev_initialize(struct device *port)
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{
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return 0;
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}
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DEVICE_AND_API_INIT(pmux_dev, CONFIG_PINMUX_DEV_NAME,
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&pinmux_dev_initialize, NULL, NULL,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&api_funcs);
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