60 lines
1.6 KiB
YAML
60 lines
1.6 KiB
YAML
# Copyright (c) 2020 Henrik Brix Andersen <henrik@brixandersen.dk>
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# SPDX-License-Identifier: Apache-2.0
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description: Xilinx AXI Quad SPI IP node
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compatible: "xlnx,xps-spi-2.00.a"
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include: spi-controller.yaml
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# Property names correspond to a subset of those generated by
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# https://github.com/Xilinx/device-tree-xlnx
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properties:
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reg:
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required: true
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interrupts:
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required: true
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xlnx,num-ss-bits:
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type: int
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required: true
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enum:
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- 1
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- 2
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- 3
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- 4
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description: |
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Number of slave select bits implemented
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xlnx,num-transfer-bits:
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type: int
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required: true
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enum:
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- 8
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- 16
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- 32
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description: |
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Number of bits per transfer
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xlnx,startup-block:
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type: boolean
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description: |
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Indicates the core is instantiated with the STARTUP block option, as is
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typically used when interfacing with the FPGA's configuration flash
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device. In this configuration the SPI clock is routed through the
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STARTUP block rather than normal signal routing.
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In this case, a workaround is required to issue a dummy
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transaction to the SPI flash device to ensure the STARTUP block is
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disengaged and allow the SPI core to control the CCLK line properly.
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The dummy READ_ID transaction will be issued to chip select 0.
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fifo-size:
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type: int
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description: |
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FIFO size configured in SPI core. 0 indicates no FIFO.
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If not specified, 0 is assumed.
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Used to optimize TX/RX read handling. If the FIFO size is 0, the driver
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will check for FIFO full/empty after every word.
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