39 lines
888 B
Plaintext
39 lines
888 B
Plaintext
/*
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* Copyright 2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define TXQ23_SIZE 0x1080
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#define SMU1_SIZE DT_REG_SIZE(DT_NODELABEL(smu1_data))
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#define SMU2_SIZE DT_REG_SIZE(DT_NODELABEL(smu2_data))
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.SMU1 (NOLOAD) :
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{
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. = ALIGN(4);
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/* CPU3 <-> CPU1 mailbox */
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*(.smu_cpu13_mbox)
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KEEP (*(.smu_cpu13_mbox))
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/* CPU3 -> CPU1 TXQ */
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*(.smu_cpu31_txq)
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KEEP (*(.smu_cpu31_txq))
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/* Left space is reserved for CPU3/CPU1 operations */
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. += SMU1_SIZE - .;
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} > SMU1
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.SMU2 (NOLOAD) :
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{
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. = ALIGN(4);
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/* CPU3 <-> CPU2 mailbox */
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*(.smu_cpu23_mbox)
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KEEP (*(.smu_cpu23_mbox))
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/* Reserve space for CPU1 -> CPU3 TXQ (allocated by the CPU2) */
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. += TXQ23_SIZE;
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/* CPU3 -> CPU2 TXQ */
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*(.smu_cpu32_txq)
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KEEP (*(.smu_cpu32_txq))
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/* Left space is reserved for CPU3/CPU2 operations */
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. += SMU2_SIZE - .;
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} > SMU2
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