251 lines
7.3 KiB
Plaintext
251 lines
7.3 KiB
Plaintext
# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_IT8XXX2
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select CPU_HAS_FPU if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "zephyr" || RISCV_ISA_EXT_M
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select HAS_PM
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select ARCH_HAS_CUSTOM_CPU_IDLE
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select ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE
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if SOC_SERIES_IT8XXX2
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config SOC_IT8XXX2
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select RISCV
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select ATOMIC_OPERATIONS_BUILTIN
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select RISCV_ISA_RV32I
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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# Workaround mul instruction bug, see:
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# https://www.ite.com.tw/uploads/product_download/it81202-bx-chip-errata.pdf
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select RISCV_ISA_EXT_M if !(SOC_IT81302BX || SOC_IT81202BX)
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select RISCV_ISA_EXT_A
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select RISCV_ISA_EXT_C
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config SOC_IT8XXX2_REG_SET_V1
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bool
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help
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This option is selected by a variable of which soc, and will
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determine the register for the IT81xx2 specification.
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config SOC_IT8XXX2_REG_SET_V2
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bool
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help
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This option is selected by a variable of which soc, and will
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determine the register for the IT82xx2 specification.
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config SOC_IT8XXX2_USBPD_PHY_V1
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bool
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help
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This option is automatically selected by variant soc and sets
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the USBPD PHY version.
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config SOC_IT8XXX2_USBPD_PHY_V2
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bool
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help
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This option is automatically selected by variant soc and sets
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the USBPD PHY version.
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config SOC_IT81302BX
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select SOC_IT8XXX2_REG_SET_V1
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select SOC_IT8XXX2_USBPD_PHY_V1
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config SOC_IT81202BX
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select SOC_IT8XXX2_REG_SET_V1
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select SOC_IT8XXX2_USBPD_PHY_V1
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config SOC_IT81302CX
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select SOC_IT8XXX2_REG_SET_V1
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select SOC_IT8XXX2_USBPD_PHY_V2
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config SOC_IT81202CX
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select SOC_IT8XXX2_REG_SET_V1
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select SOC_IT8XXX2_USBPD_PHY_V2
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config SOC_IT81302DX
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select SOC_IT8XXX2_REG_SET_V1
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select SOC_IT8XXX2_USBPD_PHY_V2
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config SOC_IT81202DX
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select SOC_IT8XXX2_REG_SET_V1
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select SOC_IT8XXX2_USBPD_PHY_V2
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config SOC_IT82202AX
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select SOC_IT8XXX2_REG_SET_V2
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select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED
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select SOC_IT8XXX2_USBPD_PHY_V2
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config SOC_IT82302AX
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select SOC_IT8XXX2_REG_SET_V2
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select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED
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select SOC_IT8XXX2_USBPD_PHY_V2
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config SOC_IT82002AW
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select SOC_IT8XXX2_REG_SET_V2
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select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED
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select SOC_IT8XXX2_USBPD_PHY_V2
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config SOC_IT82002BW
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select SOC_IT8XXX2_REG_SET_V2
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select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED
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select SOC_IT8XXX2_USBPD_PHY_V2
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config SOC_IT82202BW
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select SOC_IT8XXX2_REG_SET_V2
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select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED
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select SOC_IT8XXX2_USBPD_PHY_V2
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config SOC_IT82302BW
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select SOC_IT8XXX2_REG_SET_V2
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select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED
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select SOC_IT8XXX2_USBPD_PHY_V2
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config SOC_IT8XXX2_PLL_FLASH_48M
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bool "Flash frequency is 48MHz"
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default y
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select FLASH
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help
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Change frequency of PLL, CPU, and flash to 48MHz during initialization.
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Set n to use the default settings.
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(PLL and CPU run at 48MHz, flash frequency is 16MHz)
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config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN
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bool "The pins of GPIO group K and L aren't bonding with pad"
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default y
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help
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On IT81202 (128-pins package), the pins of GPIO group K and L aren't
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bonding with pad. So we configure these pins as internal pull-down
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at default to prevent leakage current due to floating.
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config SOC_IT8XXX2_GPIO_H7_DEFAULT_OUTPUT_LOW
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bool "The GPIOH7 isn't bonding with pad and is left floating internally"
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default y
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help
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On IT81202/IT81302, the GPIOH7 isn't bonding with pad and is left
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floating internally. We need to enable internal pull-down for the pin
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to prevent leakage current, but IT81202/IT81302 doesn't have the
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capability to pull it down. We can only set it as output low,
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so we enable output low for it at initialization to prevent leakage.
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config SOC_IT8XXX2_CPU_IDLE_GATING
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bool
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help
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This option determines whether the entering CPU idle mode can be
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gated by individual drivers. When this option is disabled, CPU idle
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mode is always permitted.
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config SOC_IT8XXX2_EC_BUS_24MHZ
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bool "EC bus is 24MHz"
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help
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Raise EC bus to 24MHz (default is 8MHz).
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This reduces read/write EC registers latency by 50%.
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NOTE: There is limitation to enabling this config on it81xx2 series.
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The clock_frequency of ite,it8xxx2-i2c node (i2c0, i2c1, and i2c2) will
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be fixed at 400KHz.
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config SOC_IT8XXX2_JTAG_DEBUG_INTERFACE
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bool "JTAG debug interface"
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help
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If enabled, the below five pins are configured as JTAG debug interface:
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- GPIOA0 -> TCK
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- GPIOA1 -> TDI
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- GPIOA4 -> TDO
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- GPIOA5 -> TMS
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- GPIOA6 -> TRST
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Supported I/O voltage is 3.3V.
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config SOC_IT8XXX2_LCVCO
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bool "LCVCO calibration"
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depends on SOC_IT8XXX2_INT_32K
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help
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The LCVCO is a highly precise clock controller used for
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calibrating the frequency shift of the PLL. Enabling this
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option allows for supported LCVCO calibration, improving
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the accuracy of the USB clock.
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choice
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prompt "Clock source for PLL reference clock"
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config SOC_IT8XXX2_INT_32K
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bool "Use the +/-2.3% internal clock generator"
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config SOC_IT8XXX2_EXT_32K
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bool "Use external 32.768 kHz clock source"
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endchoice
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config SOC_IT8XXX2_USE_ILM
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bool
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default y
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help
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If enabled, Instruction Local Memory (ILM) will be configured to execute
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code placed in the .__ram_code section out of RAM. This consumes RAM in
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blocks of 4 kilobytes, but performance of code in ILM is much more
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predictable than executing from Flash directly, and some code (such as code
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that writes to the internal Flash) must execute out of RAM.
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config SOC_IT8XXX2_EXCEPTIONS_IN_RAM
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bool "Place exception handling code in RAM"
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default y
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select SOC_IT8XXX2_USE_ILM
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help
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Place exception handling (ISR entry/exit and related) code in ILM, which
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has more reliable performance characteristics than executing directly from
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Flash. This can significantly improve performance when under I-cache
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pressure.
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config SOC_IT8XXX2_LIBRARY_TO_RAM
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bool
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help
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If this is selected it means that there is a library that needs to be excluded
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from the text section.
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config SOC_IT8XXX2_SERIAL_IN_RAM
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bool "Place serial handling code in RAM"
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select SOC_IT8XXX2_USE_ILM
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select SOC_IT8XXX2_LIBRARY_TO_RAM
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help
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Place serial handling (Include uart_ns16550.c and uart_ite_it8xxx2.c) code
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in ILM. This can improve performance.
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config SOC_IT8XXX2_KERNEL_IN_RAM
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bool "Place kernel handling code in RAM"
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select SOC_IT8XXX2_USE_ILM
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select SOC_IT8XXX2_LIBRARY_TO_RAM
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help
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Place kernel handling code in ILM. This can significantly improve performance.
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config SOC_IT8XXX2_ZEPHYR_IN_RAM
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bool "Place zephyr handling code in RAM"
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select SOC_IT8XXX2_USE_ILM
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select SOC_IT8XXX2_LIBRARY_TO_RAM
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help
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Place zephyr handling code in ILM. This can significantly improve performance.
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config SOC_IT8XXX2_SHA256_HW_ACCELERATE
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bool "HW SHA256 calculation"
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help
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IT8XXX2 HW support sha256 calculation, and its calculation is faster than FW.
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We place SHA256 message, hash and key data (total 512bytes) in RAM.
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If we enable this config, because HW limits, the sha256 data must place in
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first 4KB of RAM.
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config SOC_IT8XXX2_SHA256_BLOCK_SIZE
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hex
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default 0x500 if SOC_IT8XXX2_REG_SET_V2
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default 0x200
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DT_CHOSEN_ZEPHYR_FLASH := zephyr,flash
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config SOC_IT8XXX2_FLASH_SIZE_BYTES
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hex
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default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_ZEPHYR_FLASH))
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help
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Total size of writable flash.
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config ILM_MAX_SIZE
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int "ILM Size in kB"
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default SRAM_SIZE
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endif # SOC_SERIES_IT8XXX2
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