38 lines
808 B
C
38 lines
808 B
C
/*
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* Copyright (c) 2018-2023, Intel Corporation
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* Copyright (c) 2010-2015, Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Board configuration macros for the Alder Lake SoC
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*
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* This header file is used to specify and describe soc-level aspects for
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* the 'Alder Lake' SoC.
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*/
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#ifndef __SOC_H_
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#define __SOC_H_
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#include <zephyr/sys/util.h>
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#ifndef _ASMLANGUAGE
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#include <zephyr/device.h>
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#include <zephyr/random/random.h>
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#endif
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#ifdef CONFIG_GPIO_INTEL
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#include "soc_gpio.h"
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#endif
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#if DT_ON_BUS(DT_CHOSEN(zephyr_console), pcie)
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#include <zephyr/drivers/pcie/pcie.h>
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#define X86_SOC_EARLY_SERIAL_PCIDEV PCIE_BDF(0, 0x19, 2) /* uart2 */
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#else
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#define X86_SOC_EARLY_SERIAL_MMIO8_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_console))
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#endif
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#endif /* __SOC_H_ */
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