117 lines
3.4 KiB
Tcl
117 lines
3.4 KiB
Tcl
# Copyright (C) 2019-2020 Synopsys, Inc.
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# SPDX-License-Identifier: Apache-2.0
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#
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# Configure JTAG cable
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# SDP has built-in FT2232 chip, which is similar to Digilent HS-1, except that
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# it uses channel B for JTAG, instead of channel A.
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adapter driver ftdi
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# Only specify FTDI serial number if it is specified via
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# "set _ZEPHYR_BOARD_SERIAL 12345" before reading this script
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if { [info exists _ZEPHYR_BOARD_SERIAL] } {
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adapter serial $_ZEPHYR_BOARD_SERIAL
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}
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ftdi vid_pid 0x0403 0x6010
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ftdi layout_init 0x0088 0x008b
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ftdi channel 1
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adapter speed 10000
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# ARCs supports only JTAG.
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transport select jtag
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#
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# HS Development Kit SoC.
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#
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# Contains quad-core ARC HS38.
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#
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source [find cpu/arc/hs.tcl]
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set _coreid 0
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set _dbgbase [expr {0x00000000 | ($_coreid << 13)}]
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# CHIPNAME will be used to choose core family (600, 700 or EM). As far as
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# OpenOCD is concerned EM and HS are identical.
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set _CHIPNAME arc-em
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# OpenOCD discovers JTAG TAPs in reverse order.
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set _TARGETNAME4 $_CHIPNAME.cpu4
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jtag newtap $_CHIPNAME cpu4 -irlen 4 -ircapture 0x1 -expected-id 0x200c24b1
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set _TARGETNAME3 $_CHIPNAME.cpu3
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jtag newtap $_CHIPNAME cpu3 -irlen 4 -ircapture 0x1 -expected-id 0x200824b1
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set _TARGETNAME2 $_CHIPNAME.cpu2
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jtag newtap $_CHIPNAME cpu2 -irlen 4 -ircapture 0x1 -expected-id 0x200424b1
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set _TARGETNAME1 $_CHIPNAME.cpu1
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jtag newtap $_CHIPNAME cpu1 -irlen 4 -ircapture 0x1 -expected-id 0x200024b1
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################################
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# ARC HS38 core 2
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################################
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target create $_TARGETNAME2 arcv2 -chain-position $_TARGETNAME2
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$_TARGETNAME2 configure -coreid $_coreid
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$_TARGETNAME2 configure -dbgbase $_dbgbase
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$_TARGETNAME2 configure -event reset-assert "arc_common_reset $_TARGETNAME2"
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set _coreid [expr {$_coreid + 1}]
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set _dbgbase [expr {0x00000000 | ($_coreid << 13)}]
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arc_hs_init_regs
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# Enable L2 cache support for core 2.
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$_TARGETNAME2 arc cache l2 auto 1
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################################
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# ARC HS38 core 3
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################################
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target create $_TARGETNAME3 arcv2 -chain-position $_TARGETNAME3
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$_TARGETNAME3 configure -coreid $_coreid
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$_TARGETNAME3 configure -dbgbase $_dbgbase
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$_TARGETNAME3 configure -event reset-assert "arc_common_reset $_TARGETNAME3"
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set _coreid [expr {$_coreid + 1}]
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set _dbgbase [expr {0x00000000 | ($_coreid << 13)}]
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arc_hs_init_regs
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# Enable L2 cache support for core 3.
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$_TARGETNAME3 arc cache l2 auto 1
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################################
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# ARC HS38 core 4
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################################
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target create $_TARGETNAME4 arcv2 -chain-position $_TARGETNAME4
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$_TARGETNAME4 configure -coreid $_coreid
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$_TARGETNAME4 configure -dbgbase $_dbgbase
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# Flush L2$.
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$_TARGETNAME4 configure -event reset-assert "arc_hs_reset $_TARGETNAME4"
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set _coreid [expr {$_coreid + 1}]
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set _dbgbase [expr {0x00000000 | ($_coreid << 13)}]
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arc_hs_init_regs
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# Enable L2 cache support for core 4.
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$_TARGETNAME4 arc cache l2 auto 1
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################################
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# ARC HS38 core 1
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################################
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target create $_TARGETNAME1 arcv2 -chain-position $_TARGETNAME1
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$_TARGETNAME1 configure -coreid $_coreid
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$_TARGETNAME1 configure -dbgbase $_dbgbase
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$_TARGETNAME1 configure -event reset-assert "arc_common_reset $_TARGETNAME1"
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set _coreid [expr {$_coreid + 1}]
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set _dbgbase [expr {0x00000000 | ($_coreid << 13)}]
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arc_hs_init_regs
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# Enable L2 cache support for core 1.
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$_TARGETNAME1 arc cache l2 auto 1
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target smp $_TARGETNAME1 $_TARGETNAME2 $_TARGETNAME3 $_TARGETNAME4
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# vi:ft=tcl
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