385 lines
9.9 KiB
C
385 lines
9.9 KiB
C
/*
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* Copyright (c) 2014-2015 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file
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* @brief ARC Timer0 device driver
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*
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* This module implements a kernel device driver for the ARCv2 processor Timer0
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* and provides the standard "system clock driver" interfaces.
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*
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* If the TICKLESS_IDLE kernel configuration option is enabled, the timer may
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* be programmed to wake the system in N >= TICKLESS_IDLE_THRESH ticks. The
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* kernel invokes _timer_idle_enter() to program the up counter to trigger an
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* interrupt in N ticks. When the timer expires (or when another interrupt is
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* detected), the kernel's interrupt stub invokes _timer_idle_exit() to leave
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* the tickless idle state.
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*
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* @internal
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* The ARCv2 processor timer provides a 32-bit incrementing, wrap-to-zero
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* counter.
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*
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* Factors that increase the driver's tickless idle complexity:
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* 1. As the Timer0 up-counter is a 32-bit value, the number of ticks for which
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* the system can be in tickless idle is limited to 'max_system_ticks'.
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*
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* 2. The act of entering tickless idle may potentially straddle a tick
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* boundary. This can be detected in _timer_idle_enter() after Timer0 is
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* programmed with the new limit and acted upon in _timer_idle_exit().
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*
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* 3. Tickless idle may be prematurely aborted due to a straddled tick. See
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* previous factor.
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*
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* 4. Tickless idle may end naturally. This is detected and handled in
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* _timer_idle_exit().
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*
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* 5. Tickless idle may be prematurely aborted due to a non-timer interrupt.
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* If this occurs, Timer0 is reprogrammed to trigger at the next tick.
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* @endinternal
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*/
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#include <nanokernel.h>
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#include <arch/cpu.h>
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#include <toolchain.h>
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#include <sections.h>
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#include <misc/__assert.h>
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#include <arch/arc/v2/aux_regs.h>
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#include <sys_clock.h>
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#include <drivers/system_timer.h>
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#include <stdbool.h>
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/*
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* A board support package's board.h header must provide definitions for the
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* following constants:
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*
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* CONFIG_ARCV2_TIMER0_CLOCK_FREQ
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*
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* This is the sysTick input clock frequency.
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*/
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#include <board.h>
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#define _ARC_V2_TMR_CTRL_IE 0x1 /* interrupt enable */
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#define _ARC_V2_TMR_CTRL_NH 0x2 /* count only while not halted */
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#define _ARC_V2_TMR_CTRL_W 0x4 /* watchdog mode enable */
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#define _ARC_V2_TMR_CTRL_IP 0x8 /* interrupt pending flag */
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/* running total of timer count */
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static uint32_t __noinit cycles_per_tick;
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static uint32_t accumulated_cycle_count;
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#ifdef CONFIG_TICKLESS_IDLE
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static uint32_t __noinit max_system_ticks;
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static uint32_t __noinit programmed_limit;
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static uint32_t __noinit programmed_ticks;
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static bool straddled_tick_on_idle_enter = false;
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#endif
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/**
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*
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* @brief Get contents of Timer0 count register
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*
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* @return Current Timer0 count
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*/
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static ALWAYS_INLINE uint32_t timer0_count_register_get(void)
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{
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return _arc_v2_aux_reg_read(_ARC_V2_TMR0_COUNT);
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}
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/**
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*
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* @brief Set Timer0 count register to the specified value
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*
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* @return N/A
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*/
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static ALWAYS_INLINE void timer0_count_register_set(uint32_t value)
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{
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_arc_v2_aux_reg_write(_ARC_V2_TMR0_COUNT, value);
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}
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/**
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*
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* @brief Get contents of Timer0 control register
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*
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* @return N/A
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*/
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static ALWAYS_INLINE uint32_t timer0_control_register_get(void)
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{
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return _arc_v2_aux_reg_read(_ARC_V2_TMR0_CONTROL);
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}
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/**
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*
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* @brief Set Timer0 control register to the specified value
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*
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* @return N/A
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*/
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static ALWAYS_INLINE void timer0_control_register_set(uint32_t value)
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{
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_arc_v2_aux_reg_write(_ARC_V2_TMR0_CONTROL, value);
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}
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/**
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*
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* @brief Set Timer0 limit register to the specified value
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*
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* @return N/A
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*/
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static ALWAYS_INLINE void timer0_limit_register_set(uint32_t count)
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{
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_arc_v2_aux_reg_write(_ARC_V2_TMR0_LIMIT, count);
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}
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#ifdef CONFIG_TICKLESS_IDLE
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static ALWAYS_INLINE void update_accumulated_count(void)
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{
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accumulated_cycle_count += (_sys_idle_elapsed_ticks * cycles_per_tick);
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}
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#else /* CONFIG_TICKLESS_IDLE */
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static ALWAYS_INLINE void update_accumulated_count(void)
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{
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accumulated_cycle_count += cycles_per_tick;
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}
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#endif /* CONFIG_TICKLESS_IDLE */
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/**
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*
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* @brief System clock periodic tick handler
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*
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* This routine handles the system clock periodic tick interrupt. It always
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* announces one tick.
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*
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* @return N/A
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*/
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void _timer_int_handler(void *unused)
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{
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ARG_UNUSED(unused);
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/* clear the interrupt by writing 0 to IP bit of the control register */
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timer0_control_register_set(_ARC_V2_TMR_CTRL_NH | _ARC_V2_TMR_CTRL_IE);
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#if defined(CONFIG_TICKLESS_IDLE)
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timer0_limit_register_set(cycles_per_tick - 1);
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_sys_idle_elapsed_ticks = 1;
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#endif
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update_accumulated_count();
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_sys_clock_tick_announce();
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}
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#if defined(CONFIG_TICKLESS_IDLE)
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/*
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* @brief initialize the tickless idle feature
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*
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* This routine initializes the tickless idle feature.
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*
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* @return N/A
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*/
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static void tickless_idle_init(void)
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{
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/* calculate the max number of ticks with this 32-bit H/W counter */
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max_system_ticks = 0xffffffff / cycles_per_tick;
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}
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/*
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* @brief Place the system timer into idle state
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*
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* Re-program the timer to enter into the idle state for either the given
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* number of ticks or the maximum number of ticks that can be programmed
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* into hardware.
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*
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* @return N/A
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*/
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void _timer_idle_enter(int32_t ticks)
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{
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uint32_t status;
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if ((ticks == TICKS_UNLIMITED) || (ticks > max_system_ticks)) {
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/*
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* The number of cycles until the timer must fire next might not fit
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* in the 32-bit counter register. To work around this, program
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* the counter to fire in the maximum number of ticks.
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*/
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ticks = max_system_ticks;
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}
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programmed_ticks = ticks;
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programmed_limit = (programmed_ticks * cycles_per_tick);
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timer0_limit_register_set(programmed_limit);
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/*
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* If Timer0's IP bit is set, then it is known that we have straddled
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* a tick boundary while entering tickless idle.
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*/
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status = timer0_control_register_get();
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if (status & _ARC_V2_TMR_CTRL_IP) {
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straddled_tick_on_idle_enter = true;
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}
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}
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/*
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* @brief handling of tickless idle when interrupted
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*
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* The routine, called by _SysPowerSaveIdleExit, is responsible for taking the
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* timer out of idle mode and generating an interrupt at the next tick
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* interval. It is expected that interrupts have been disabled.
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*
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* RETURNS: N/A
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*/
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void _timer_idle_exit(void)
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{
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if (straddled_tick_on_idle_enter) {
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/* Aborting the tickless idle due to a straddled tick. */
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straddled_tick_on_idle_enter = false;
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return;
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}
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uint32_t control;
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uint32_t current_count;
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current_count = timer0_count_register_get();
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control = timer0_control_register_get();
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if (control & _ARC_V2_TMR_CTRL_IP) {
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/*
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* The timer has expired. The handler _timer_int_handler() is
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* guaranteed to execute. Track the number of elapsed ticks. The
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* handler _timer_int_handler() will account for the final tick.
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*/
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_sys_idle_elapsed_ticks = programmed_ticks - 1;
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update_accumulated_count();
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_sys_clock_tick_announce();
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return;
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}
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/*
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* A non-timer interrupt occurred. Announce any
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* ticks that have elapsed during the tickless idle.
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*/
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uint32_t remaining_cycles = programmed_limit - current_count;
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_sys_idle_elapsed_ticks = current_count / cycles_per_tick;
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if (_sys_idle_elapsed_ticks > 0) {
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update_accumulated_count();
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_sys_clock_tick_announce();
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}
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/*
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* Ensure the timer will expire at the end of the next tick in case
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* the ISR makes any tasks and/or fibers ready to run.
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*/
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if (remaining_cycles >= cycles_per_tick) {
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timer0_count_register_set(programmed_limit -
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((remaining_cycles - 1) % cycles_per_tick) - 1);
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}
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}
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#else
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static void tickless_idle_init(void) {}
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#endif /* CONFIG_TICKLESS_IDLE */
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/**
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*
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* @brief Initialize and enable the system clock
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*
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* This routine is used to program the ARCv2 timer to deliver interrupts at the
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* rate specified via the 'sys_clock_us_per_tick' global variable.
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*
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* @return 0
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*/
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int _sys_clock_driver_init(struct device *device)
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{
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ARG_UNUSED(device);
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/* ensure that the timer will not generate interrupts */
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timer0_control_register_set(0);
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timer0_count_register_set(0);
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cycles_per_tick = sys_clock_hw_cycles_per_tick;
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IRQ_CONNECT(CONFIG_ARCV2_TIMER0_INT_LVL, CONFIG_ARCV2_TIMER0_INT_PRI,
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_timer_int_handler, 0, 0);
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/*
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* Set the reload value to achieve the configured tick rate, enable the
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* counter and interrupt generation.
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*/
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tickless_idle_init();
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timer0_limit_register_set(cycles_per_tick - 1);
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timer0_control_register_set(_ARC_V2_TMR_CTRL_NH | _ARC_V2_TMR_CTRL_IE);
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/* everything has been configured: safe to enable the interrupt */
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irq_enable(CONFIG_ARCV2_TIMER0_INT_LVL);
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return 0;
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}
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/**
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*
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* @brief Read the platform's timer hardware
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*
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* This routine returns the current time in terms of timer hardware clock
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* cycles.
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*
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* @return up counter of elapsed clock cycles
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*/
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uint32_t sys_cycle_get_32(void)
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{
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return (accumulated_cycle_count + timer0_count_register_get());
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}
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#if defined(CONFIG_SYSTEM_CLOCK_DISABLE)
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/**
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*
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* @brief Stop announcing ticks into the kernel
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*
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* This routine disables timer interrupt generation and delivery.
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* Note that the timer's counting cannot be stopped by software.
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*
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* @return N/A
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*/
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void sys_clock_disable(void)
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{
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unsigned int key; /* interrupt lock level */
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uint32_t control; /* timer control register value */
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key = irq_lock();
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/* disable interrupt generation */
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control = timer0_control_register_get();
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timer0_control_register_set(control & ~_ARC_V2_TMR_CTRL_IE);
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irq_unlock(key);
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/* disable interrupt in the interrupt controller */
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irq_disable(CONFIG_ARCV2_TIMER0_INT_LVL);
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}
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#endif /* CONFIG_SYSTEM_CLOCK_DISABLE */
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