Yong Cong Sin 4bbc2a7893 arch: riscv: isr.S: restore s0 before jumping to z_riscv_fatal_error_csf ... Restore the s0 we saved early in ISR entry so it shows up properly in the CSF. Signed-off-by: David Reiss <dreiss@meta.com> Signed-off-by: Yong Cong Sin <ycsin@meta.com>		2024-10-02 09:48:02 +02:00
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arc	…
arm	arch: Add Cortex-R8 support	2024-10-01 09:58:22 +02:00
arm64	…
common	…
mips	…
nios2	…
posix	…
riscv	arch: riscv: isr.S: restore s0 before jumping to z_riscv_fatal_error_csf	2024-10-02 09:48:02 +02:00
sparc	…
x86	arch: x86_64: re-enable -mno-red-zone	2024-09-24 10:11:15 +02:00
xtensa	LLEXT: Xtensa: add support for L32R relocation	2024-09-29 21:21:24 +02:00
CMakeLists.txt	…
Kconfig	…
Kconfig.v1	…
Kconfig.v2	…
archs.yml	…