44 lines
1.7 KiB
C
44 lines
1.7 KiB
C
/*
|
|
* Copyright (c) 2018 Synopsys, Inc. All rights reserved.
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
/* SoC level DTS fixup file */
|
|
|
|
/* CCM configuration */
|
|
#define DT_DCCM_BASE_ADDRESS DT_ARC_DCCM_80000000_BASE_ADDRESS
|
|
#define DT_DCCM_SIZE (DT_ARC_DCCM_80000000_SIZE >> 10)
|
|
|
|
#define DT_ICCM_BASE_ADDRESS DT_ARC_ICCM_60000000_BASE_ADDRESS
|
|
#define DT_ICCM_SIZE (DT_ARC_ICCM_60000000_SIZE >> 10)
|
|
|
|
/*
|
|
* UART configuration
|
|
*/
|
|
#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_F0004000_BASE_ADDRESS
|
|
#define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_F0004000_IRQ_0
|
|
#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_F0004000_CLOCK_FREQUENCY
|
|
#define DT_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_F0004000_CURRENT_SPEED
|
|
#define DT_UART_NS16550_PORT_0_NAME DT_NS16550_F0004000_LABEL
|
|
#define DT_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_F0004000_IRQ_0_PRIORITY
|
|
|
|
/*
|
|
* GPIO configuration
|
|
*/
|
|
#define DT_GPIO_DW_0_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F0002000_BASE_ADDRESS
|
|
#define DT_GPIO_DW_0_BITS DT_SNPS_DESIGNWARE_GPIO_F0002000_BITS
|
|
#define CONFIG_GPIO_DW_0_NAME DT_SNPS_DESIGNWARE_GPIO_F0002000_LABEL
|
|
#define DT_GPIO_DW_0_IRQ DT_SNPS_DESIGNWARE_GPIO_F0002000_IRQ_0
|
|
#define CONFIG_GPIO_DW_0_IRQ_PRI DT_SNPS_DESIGNWARE_GPIO_F0002000_IRQ_0_PRIORITY
|
|
#define DT_GPIO_DW_0_IRQ_FLAGS 0
|
|
|
|
#define DT_GPIO_DW_1_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F000200C_BASE_ADDRESS
|
|
#define DT_GPIO_DW_1_BITS DT_SNPS_DESIGNWARE_GPIO_F000200C_BITS
|
|
#define CONFIG_GPIO_DW_1_NAME DT_SNPS_DESIGNWARE_GPIO_F000200C_LABEL
|
|
#define DT_GPIO_DW_1_IRQ DT_SNPS_DESIGNWARE_GPIO_F000200C_IRQ_0
|
|
#define CONFIG_GPIO_DW_1_IRQ_PRI DT_SNPS_DESIGNWARE_GPIO_F000200C_IRQ_0_PRIORITY
|
|
#define DT_GPIO_DW_1_IRQ_FLAGS 0
|
|
|
|
/* End of SoC Level DTS fixup file */
|