491 lines
13 KiB
C
491 lines
13 KiB
C
/*
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* Copyright (c) 2016 Freescale Semiconductor, Inc.
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* Copyright (c) 2017, NXP
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* Copyright (c) 2018 Foundries.io
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <device.h>
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#include <gpio.h>
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#include <soc.h>
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#include <fsl_common.h>
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#include <fsl_port.h>
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#include <clock_control.h>
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#include "gpio_utils.h"
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struct gpio_rv32m1_config {
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GPIO_Type *gpio_base;
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PORT_Type *port_base;
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unsigned int flags;
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char *clock_controller;
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clock_control_subsys_t clock_subsys;
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int (*irq_config_func)(struct device *dev);
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};
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struct gpio_rv32m1_data {
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/* port ISR callback routine address */
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sys_slist_t callbacks;
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/* pin callback routine enable flags, by pin number */
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u32_t pin_callback_enables;
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};
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static int gpio_rv32m1_configure(struct device *dev,
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int access_op, u32_t pin, int flags)
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{
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const struct gpio_rv32m1_config *config = dev->config->config_info;
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GPIO_Type *gpio_base = config->gpio_base;
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PORT_Type *port_base = config->port_base;
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port_interrupt_t port_interrupt = 0;
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u32_t mask = 0U;
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u32_t pcr = 0U;
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u8_t i;
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/* Check for an invalid pin configuration */
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if ((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) {
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return -EINVAL;
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}
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/* Check if GPIO port supports interrupts */
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if ((flags & GPIO_INT) && ((config->flags & GPIO_INT) == 0U)) {
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return -EINVAL;
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}
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/* The flags contain options that require touching registers in the
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* GPIO module and the corresponding PORT module.
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*
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* Start with the GPIO module and set up the pin direction register.
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* 0 - pin is input, 1 - pin is output
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*/
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if (access_op == GPIO_ACCESS_BY_PIN) {
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if ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN) {
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gpio_base->PDDR &= ~BIT(pin);
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} else { /* GPIO_DIR_OUT */
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gpio_base->PDDR |= BIT(pin);
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}
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} else { /* GPIO_ACCESS_BY_PORT */
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if ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN) {
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gpio_base->PDDR = 0x0;
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} else { /* GPIO_DIR_OUT */
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gpio_base->PDDR = 0xFFFFFFFF;
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}
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}
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/* Now do the PORT module. Figure out the pullup/pulldown
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* configuration, but don't write it to the PCR register yet.
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*/
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mask |= PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
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if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_UP) {
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/* Enable the pull and select the pullup resistor. */
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pcr |= PORT_PCR_PE_MASK | PORT_PCR_PS_MASK;
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} else if ((flags & GPIO_PUD_MASK) == GPIO_PUD_PULL_DOWN) {
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/* Enable the pull and select the pulldown resistor (deselect
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* the pullup resistor.
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*/
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pcr |= PORT_PCR_PE_MASK;
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}
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/* Still in the PORT module. Figure out the interrupt configuration,
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* but don't write it to the PCR register yet.
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*/
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mask |= PORT_PCR_IRQC_MASK;
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if (flags & GPIO_INT) {
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if (flags & GPIO_INT_EDGE) {
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if (flags & GPIO_INT_ACTIVE_HIGH) {
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port_interrupt = kPORT_InterruptRisingEdge;
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} else if (flags & GPIO_INT_DOUBLE_EDGE) {
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port_interrupt = kPORT_InterruptEitherEdge;
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} else {
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port_interrupt = kPORT_InterruptFallingEdge;
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}
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} else { /* GPIO_INT_LEVEL */
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if (flags & GPIO_INT_ACTIVE_HIGH) {
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port_interrupt = kPORT_InterruptLogicOne;
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} else {
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port_interrupt = kPORT_InterruptLogicZero;
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}
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}
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pcr |= PORT_PCR_IRQC(port_interrupt);
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}
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mask |= PORT_PCR_MUX_MASK;
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/* Now we can write the PORT PCR register(s). If accessing by pin, we
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* only need to write one PCR register. Otherwise, write all the PCR
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* registers in the PORT module (one for each pin).
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*/
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if (access_op == GPIO_ACCESS_BY_PIN) {
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port_base->PCR[pin] = (port_base->PCR[pin] & ~mask) | pcr |
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PORT_PCR_MUX(kPORT_MuxAsGpio);
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} else { /* GPIO_ACCESS_BY_PORT */
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for (i = 0U; i < ARRAY_SIZE(port_base->PCR); i++) {
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port_base->PCR[i] = (port_base->PCR[pin] & ~mask) | pcr
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| PORT_PCR_MUX(kPORT_MuxAsGpio);
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}
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}
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return 0;
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}
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static int gpio_rv32m1_write(struct device *dev,
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int access_op, u32_t pin, u32_t value)
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{
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const struct gpio_rv32m1_config *config = dev->config->config_info;
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GPIO_Type *gpio_base = config->gpio_base;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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if (value) {
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/* Set the data output for the corresponding pin.
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* Writing zeros to the other bits leaves the data
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* output unchanged for the other pins.
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*/
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gpio_base->PSOR = BIT(pin);
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} else {
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/* Clear the data output for the corresponding pin.
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* Writing zeros to the other bits leaves the data
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* output unchanged for the other pins.
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*/
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gpio_base->PCOR = BIT(pin);
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}
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} else { /* GPIO_ACCESS_BY_PORT */
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/* Write the data output for all the pins */
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gpio_base->PDOR = value;
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}
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return 0;
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}
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static int gpio_rv32m1_read(struct device *dev,
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int access_op, u32_t pin, u32_t *value)
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{
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const struct gpio_rv32m1_config *config = dev->config->config_info;
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GPIO_Type *gpio_base = config->gpio_base;
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*value = gpio_base->PDIR;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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*value = (*value & BIT(pin)) >> pin;
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}
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/* nothing more to do for GPIO_ACCESS_BY_PORT */
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return 0;
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}
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static int gpio_rv32m1_manage_callback(struct device *dev,
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struct gpio_callback *callback, bool set)
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{
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struct gpio_rv32m1_data *data = dev->driver_data;
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gpio_manage_callback(&data->callbacks, callback, set);
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return 0;
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}
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static int gpio_rv32m1_enable_callback(struct device *dev,
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int access_op, u32_t pin)
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{
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struct gpio_rv32m1_data *data = dev->driver_data;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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data->pin_callback_enables |= BIT(pin);
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} else {
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data->pin_callback_enables = 0xFFFFFFFF;
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}
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return 0;
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}
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static int gpio_rv32m1_disable_callback(struct device *dev,
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int access_op, u32_t pin)
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{
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struct gpio_rv32m1_data *data = dev->driver_data;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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data->pin_callback_enables &= ~BIT(pin);
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} else {
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data->pin_callback_enables = 0U;
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}
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return 0;
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}
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static void gpio_rv32m1_port_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
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const struct gpio_rv32m1_config *config = dev->config->config_info;
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struct gpio_rv32m1_data *data = dev->driver_data;
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u32_t enabled_int, int_status;
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int_status = config->port_base->ISFR;
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enabled_int = int_status & data->pin_callback_enables;
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gpio_fire_callbacks(&data->callbacks, dev, enabled_int);
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/* Clear the port interrupts */
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config->port_base->ISFR = 0xFFFFFFFF;
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}
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static int gpio_rv32m1_init(struct device *dev)
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{
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const struct gpio_rv32m1_config *config = dev->config->config_info;
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struct device *clk;
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int ret;
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if (config->clock_controller) {
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clk = device_get_binding(config->clock_controller);
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if (!clk) {
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return -ENODEV;
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}
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ret = clock_control_on(clk, config->clock_subsys);
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if (ret < 0) {
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return ret;
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}
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}
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return config->irq_config_func(dev);
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}
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static const struct gpio_driver_api gpio_rv32m1_driver_api = {
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.config = gpio_rv32m1_configure,
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.write = gpio_rv32m1_write,
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.read = gpio_rv32m1_read,
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.manage_callback = gpio_rv32m1_manage_callback,
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.enable_callback = gpio_rv32m1_enable_callback,
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.disable_callback = gpio_rv32m1_disable_callback,
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};
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#ifdef CONFIG_GPIO_RV32M1_PORTA
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static int gpio_rv32m1_porta_init(struct device *dev);
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static const struct gpio_rv32m1_config gpio_rv32m1_porta_config = {
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.gpio_base = (GPIO_Type *) DT_OPENISA_RV32M1_GPIO_GPIO_A_BASE_ADDRESS,
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.port_base = PORTA,
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#ifdef DT_OPENISA_RV32M1_GPIO_GPIO_A_IRQ
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.flags = GPIO_INT,
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#else
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.flags = 0,
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#endif
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.irq_config_func = gpio_rv32m1_porta_init,
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#ifdef DT_OPENISA_RV32M1_GPIO_GPIO_A_CLOCK_CONTROLLER
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.clock_controller = DT_OPENISA_RV32M1_GPIO_GPIO_A_CLOCK_CONTROLLER,
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.clock_subsys = (clock_control_subsys_t)
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DT_OPENISA_RV32M1_GPIO_GPIO_A_CLOCK_NAME,
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#else
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.clock_controller = NULL,
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#endif
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};
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static struct gpio_rv32m1_data gpio_rv32m1_porta_data;
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DEVICE_AND_API_INIT(gpio_rv32m1_porta, DT_OPENISA_RV32M1_GPIO_GPIO_A_LABEL,
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gpio_rv32m1_init,
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&gpio_rv32m1_porta_data, &gpio_rv32m1_porta_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&gpio_rv32m1_driver_api);
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static int gpio_rv32m1_porta_init(struct device *dev)
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{
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#ifdef DT_OPENISA_RV32M1_GPIO_GPIO_A_IRQ
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IRQ_CONNECT(DT_OPENISA_RV32M1_GPIO_GPIO_A_IRQ,
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DT_OPENISA_RV32M1_GPIO_GPIO_A_IRQ_PRIORITY,
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gpio_rv32m1_port_isr, DEVICE_GET(gpio_rv32m1_porta), 0);
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irq_enable(DT_OPENISA_RV32M1_GPIO_GPIO_A_IRQ);
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return 0;
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#else
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return -1;
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#endif
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}
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#endif /* CONFIG_GPIO_RV32M1_PORTA */
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#ifdef CONFIG_GPIO_RV32M1_PORTB
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static int gpio_rv32m1_portb_init(struct device *dev);
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static const struct gpio_rv32m1_config gpio_rv32m1_portb_config = {
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.gpio_base = (GPIO_Type *) DT_OPENISA_RV32M1_GPIO_GPIO_B_BASE_ADDRESS,
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.port_base = PORTB,
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#ifdef DT_OPENISA_RV32M1_GPIO_GPIO_B_IRQ
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.flags = GPIO_INT,
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#else
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.flags = 0,
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#endif
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.irq_config_func = gpio_rv32m1_portb_init,
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#ifdef DT_OPENISA_RV32M1_GPIO_GPIO_B_CLOCK_CONTROLLER
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.clock_controller = DT_OPENISA_RV32M1_GPIO_GPIO_B_CLOCK_CONTROLLER,
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.clock_subsys = (clock_control_subsys_t)
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DT_OPENISA_RV32M1_GPIO_GPIO_B_CLOCK_NAME,
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#else
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.clock_controller = NULL,
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#endif
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};
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static struct gpio_rv32m1_data gpio_rv32m1_portb_data;
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DEVICE_AND_API_INIT(gpio_rv32m1_portb, DT_OPENISA_RV32M1_GPIO_GPIO_B_LABEL,
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gpio_rv32m1_init,
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&gpio_rv32m1_portb_data, &gpio_rv32m1_portb_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&gpio_rv32m1_driver_api);
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static int gpio_rv32m1_portb_init(struct device *dev)
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{
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#ifdef DT_OPENISA_RV32M1_GPIO_GPIO_B_IRQ
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IRQ_CONNECT(DT_OPENISA_RV32M1_GPIO_GPIO_B_IRQ,
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DT_OPENISA_RV32M1_GPIO_GPIO_B_IRQ_PRIORITY,
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gpio_rv32m1_port_isr, DEVICE_GET(gpio_rv32m1_portb), 0);
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irq_enable(DT_OPENISA_RV32M1_GPIO_GPIO_B_IRQ);
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return 0;
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#else
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return -1;
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#endif
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}
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#endif /* CONFIG_GPIO_RV32M1_PORTB */
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#ifdef CONFIG_GPIO_RV32M1_PORTC
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static int gpio_rv32m1_portc_init(struct device *dev);
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static const struct gpio_rv32m1_config gpio_rv32m1_portc_config = {
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.gpio_base = (GPIO_Type *) DT_OPENISA_RV32M1_GPIO_GPIO_C_BASE_ADDRESS,
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.port_base = PORTC,
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#ifdef DT_OPENISA_RV32M1_GPIO_GPIO_C_IRQ
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.flags = GPIO_INT,
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#else
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.flags = 0,
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#endif
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.irq_config_func = gpio_rv32m1_portc_init,
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#ifdef DT_OPENISA_RV32M1_GPIO_GPIO_C_CLOCK_CONTROLLER
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.clock_controller = DT_OPENISA_RV32M1_GPIO_GPIO_C_CLOCK_CONTROLLER,
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.clock_subsys = (clock_control_subsys_t)
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DT_OPENISA_RV32M1_GPIO_GPIO_C_CLOCK_NAME,
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#else
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.clock_controller = NULL,
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#endif
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};
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static struct gpio_rv32m1_data gpio_rv32m1_portc_data;
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DEVICE_AND_API_INIT(gpio_rv32m1_portc, DT_OPENISA_RV32M1_GPIO_GPIO_C_LABEL,
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gpio_rv32m1_init,
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&gpio_rv32m1_portc_data, &gpio_rv32m1_portc_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&gpio_rv32m1_driver_api);
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static int gpio_rv32m1_portc_init(struct device *dev)
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{
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#ifdef DT_OPENISA_RV32M1_GPIO_GPIO_C_IRQ
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IRQ_CONNECT(DT_OPENISA_RV32M1_GPIO_GPIO_C_IRQ,
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DT_OPENISA_RV32M1_GPIO_GPIO_C_IRQ_PRIORITY,
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gpio_rv32m1_port_isr, DEVICE_GET(gpio_rv32m1_portc), 0);
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irq_enable(DT_OPENISA_RV32M1_GPIO_GPIO_C_IRQ);
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return 0;
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#else
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return -1;
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#endif
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}
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#endif /* CONFIG_GPIO_RV32M1_PORTC */
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#ifdef CONFIG_GPIO_RV32M1_PORTD
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static int gpio_rv32m1_portd_init(struct device *dev);
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static const struct gpio_rv32m1_config gpio_rv32m1_portd_config = {
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.gpio_base = (GPIO_Type *) DT_OPENISA_RV32M1_GPIO_GPIO_D_BASE_ADDRESS,
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.port_base = PORTD,
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#ifdef DT_OPENISA_RV32M1_GPIO_GPIO_D_IRQ
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.flags = GPIO_INT,
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#else
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.flags = 0,
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#endif
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.irq_config_func = gpio_rv32m1_portd_init,
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#ifdef DT_OPENISA_RV32M1_GPIO_GPIO_D_CLOCK_CONTROLLER
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.clock_controller = DT_OPENISA_RV32M1_GPIO_GPIO_D_CLOCK_CONTROLLER,
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.clock_subsys = (clock_control_subsys_t)
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DT_OPENISA_RV32M1_GPIO_GPIO_D_CLOCK_NAME,
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#else
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.clock_controller = NULL,
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#endif
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};
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static struct gpio_rv32m1_data gpio_rv32m1_portd_data;
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DEVICE_AND_API_INIT(gpio_rv32m1_portd, DT_OPENISA_RV32M1_GPIO_GPIO_D_LABEL,
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gpio_rv32m1_init,
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&gpio_rv32m1_portd_data, &gpio_rv32m1_portd_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&gpio_rv32m1_driver_api);
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static int gpio_rv32m1_portd_init(struct device *dev)
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{
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#ifdef DT_OPENISA_RV32M1_GPIO_GPIO_D_IRQ
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IRQ_CONNECT(DT_OPENISA_RV32M1_GPIO_GPIO_D_IRQ,
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DT_OPENISA_RV32M1_GPIO_GPIO_D_IRQ_PRIORITY,
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gpio_rv32m1_port_isr, DEVICE_GET(gpio_rv32m1_portd), 0);
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irq_enable(DT_OPENISA_RV32M1_GPIO_GPIO_D_IRQ);
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return 0;
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#else
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return -1;
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#endif
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}
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#endif /* CONFIG_GPIO_RV32M1_PORTD */
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#ifdef CONFIG_GPIO_RV32M1_PORTE
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static int gpio_rv32m1_porte_init(struct device *dev);
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static const struct gpio_rv32m1_config gpio_rv32m1_porte_config = {
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.gpio_base = (GPIO_Type *) DT_OPENISA_RV32M1_GPIO_GPIO_E_BASE_ADDRESS,
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.port_base = PORTE,
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#ifdef DT_OPENISA_RV32M1_GPIO_GPIO_E_IRQ
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.flags = GPIO_INT,
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#else
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.flags = 0,
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#endif
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.irq_config_func = gpio_rv32m1_porte_init,
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#ifdef DT_OPENISA_RV32M1_GPIO_GPIO_E_CLOCK_CONTROLLER
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.clock_controller = DT_OPENISA_RV32M1_GPIO_GPIO_E_CLOCK_CONTROLLER,
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.clock_subsys = (clock_control_subsys_t)
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DT_OPENISA_RV32M1_GPIO_GPIO_E_CLOCK_NAME,
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#else
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.clock_controller = NULL,
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#endif
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};
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static struct gpio_rv32m1_data gpio_rv32m1_porte_data;
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DEVICE_AND_API_INIT(gpio_rv32m1_porte, DT_OPENISA_RV32M1_GPIO_GPIO_E_LABEL,
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gpio_rv32m1_init,
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&gpio_rv32m1_porte_data, &gpio_rv32m1_porte_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&gpio_rv32m1_driver_api);
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static int gpio_rv32m1_porte_init(struct device *dev)
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{
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#ifdef DT_OPENISA_RV32M1_GPIO_GPIO_E_IRQ
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IRQ_CONNECT(DT_OPENISA_RV32M1_GPIO_GPIO_E_IRQ,
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DT_OPENISA_RV32M1_GPIO_GPIO_E_IRQ_PRIORITY,
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gpio_rv32m1_port_isr, DEVICE_GET(gpio_rv32m1_porte), 0);
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irq_enable(DT_OPENISA_RV32M1_GPIO_GPIO_E_IRQ);
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return 0;
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#else
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return -1;
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#endif
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}
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#endif /* CONFIG_GPIO_RV32M1_PORTE */
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