166 lines
4.6 KiB
C
166 lines
4.6 KiB
C
/*
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* Copyright (c) 2023 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ambiq_watchdog
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/watchdog.h>
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#include <errno.h>
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#include <am_mcu_apollo.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(wdt_ambiq, CONFIG_WDT_LOG_LEVEL);
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typedef void (*ambiq_wdt_cfg_func_t)(void);
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struct wdt_ambiq_config {
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uint32_t base;
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uint32_t irq_num;
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uint8_t clk_freq;
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ambiq_wdt_cfg_func_t cfg_func;
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};
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struct wdt_ambiq_data {
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wdt_callback_t callback;
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uint32_t timeout;
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bool reset;
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};
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static void wdt_ambiq_isr(void *arg)
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{
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const struct device *dev = (const struct device *)arg;
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struct wdt_ambiq_data *data = dev->data;
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uint32_t status;
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am_hal_wdt_interrupt_status_get(AM_HAL_WDT_MCU, &status, false);
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am_hal_wdt_interrupt_clear(AM_HAL_WDT_MCU, status);
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if (data->callback) {
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data->callback(dev, 0);
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}
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}
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static int wdt_ambiq_setup(const struct device *dev, uint8_t options)
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{
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const struct wdt_ambiq_config *dev_cfg = dev->config;
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struct wdt_ambiq_data *data = dev->data;
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am_hal_wdt_config_t cfg;
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if (dev_cfg->clk_freq == 128) {
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cfg.eClockSource = AM_HAL_WDT_128HZ;
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} else if (dev_cfg->clk_freq == 16) {
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cfg.eClockSource = AM_HAL_WDT_16HZ;
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} else if (dev_cfg->clk_freq == 1) {
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cfg.eClockSource = AM_HAL_WDT_1HZ;
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}
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cfg.bInterruptEnable = true;
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cfg.ui32InterruptValue = data->timeout;
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cfg.bResetEnable = data->reset;
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cfg.ui32ResetValue = data->timeout;
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cfg.bAlertOnDSPReset = false;
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am_hal_wdt_config(AM_HAL_WDT_MCU, &cfg);
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am_hal_wdt_interrupt_enable(AM_HAL_WDT_MCU, AM_HAL_WDT_INTERRUPT_MCU);
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am_hal_wdt_start(AM_HAL_WDT_MCU, false);
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return 0;
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}
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static int wdt_ambiq_disable(const struct device *dev)
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{
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ARG_UNUSED(dev);
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am_hal_wdt_stop(AM_HAL_WDT_MCU);
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return 0;
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}
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static int wdt_ambiq_install_timeout(const struct device *dev, const struct wdt_timeout_cfg *cfg)
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{
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const struct wdt_ambiq_config *dev_cfg = dev->config;
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struct wdt_ambiq_data *data = dev->data;
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if (cfg->window.min != 0U || cfg->window.max == 0U) {
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return -EINVAL;
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}
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data->timeout = cfg->window.max / 1000 * dev_cfg->clk_freq;
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data->callback = cfg->callback;
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switch (cfg->flags) {
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case WDT_FLAG_RESET_CPU_CORE:
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case WDT_FLAG_RESET_SOC:
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data->reset = true;
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break;
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case WDT_FLAG_RESET_NONE:
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data->reset = false;
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break;
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default:
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LOG_ERR("Unsupported watchdog config flag");
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return -EINVAL;
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}
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return 0;
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}
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static int wdt_ambiq_feed(const struct device *dev, int channel_id)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(channel_id);
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am_hal_wdt_restart(AM_HAL_WDT_MCU);
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LOG_DBG("Fed the watchdog");
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return 0;
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}
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static int wdt_ambiq_init(const struct device *dev)
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{
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const struct wdt_ambiq_config *dev_cfg = dev->config;
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if (dev_cfg->clk_freq != 128 && dev_cfg->clk_freq != 16 && dev_cfg->clk_freq != 1) {
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return -ENOTSUP;
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}
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NVIC_ClearPendingIRQ(dev_cfg->irq_num);
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dev_cfg->cfg_func();
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irq_enable(dev_cfg->irq_num);
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return 0;
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}
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static const struct wdt_driver_api wdt_ambiq_driver_api = {
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.setup = wdt_ambiq_setup,
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.disable = wdt_ambiq_disable,
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.install_timeout = wdt_ambiq_install_timeout,
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.feed = wdt_ambiq_feed,
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};
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#define AMBIQ_WDT_INIT(n) \
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static struct wdt_ambiq_data wdt_ambiq_data##n; \
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static void ambiq_wdt_cfg_func_##n(void) \
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{ \
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\
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IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), wdt_ambiq_isr, \
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DEVICE_DT_INST_GET(n), 0); \
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}; \
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static const struct wdt_ambiq_config wdt_ambiq_config##n = { \
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.base = DT_INST_REG_ADDR(n), \
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.clk_freq = DT_INST_PROP(n, clock_frequency), \
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.irq_num = DT_INST_IRQN(n), \
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.cfg_func = ambiq_wdt_cfg_func_##n}; \
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\
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DEVICE_DT_INST_DEFINE(n, wdt_ambiq_init, NULL, &wdt_ambiq_data##n, &wdt_ambiq_config##n, \
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&wdt_ambiq_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(AMBIQ_WDT_INIT)
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