347 lines
9.4 KiB
C
347 lines
9.4 KiB
C
/*
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* Copyright (c) 2016-2017, Texas Instruments Incorporated
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ti_cc32xx_uart
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#include <zephyr/kernel.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/drivers/uart.h>
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#include <zephyr/drivers/pinctrl.h>
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/* Driverlib includes */
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#include <inc/hw_types.h>
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#include <driverlib/rom.h>
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#include <driverlib/rom_map.h>
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#include <driverlib/prcm.h>
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#include <driverlib/uart.h>
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#include <zephyr/irq.h>
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struct uart_cc32xx_dev_config {
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unsigned long base;
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uint32_t sys_clk_freq;
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const struct pinctrl_dev_config *pcfg;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_config_func_t irq_config_func;
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#endif
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};
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struct uart_cc32xx_dev_data_t {
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uint32_t prcm;
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uint32_t baud_rate;
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_callback_user_data_t cb; /**< Callback function pointer */
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void *cb_data; /**< Callback function arg */
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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};
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#define PRIME_CHAR '\r'
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/* Forward decls: */
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static void uart_cc32xx_isr(const struct device *dev);
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#endif
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/*
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* CC32XX UART has a configurable FIFO length, from 1 to 8 characters.
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* However, the Zephyr console driver, and the Zephyr uart sample test, assume
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* a RX FIFO depth of one: meaning, one interrupt == one character received.
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* Keeping with this assumption, this driver leaves the FIFOs disabled,
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* and at depth 1.
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*/
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static int uart_cc32xx_init(const struct device *dev)
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{
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const struct uart_cc32xx_dev_config *config = dev->config;
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const struct uart_cc32xx_dev_data_t *data = dev->data;
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int ret;
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MAP_PRCMPeripheralClkEnable(data->prcm,
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PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
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MAP_PRCMPeripheralReset(data->prcm);
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ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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return ret;
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}
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/* This also calls MAP_UARTEnable() to enable the FIFOs: */
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MAP_UARTConfigSetExpClk(config->base,
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MAP_PRCMPeripheralClockGet(data->prcm),
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data->baud_rate,
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(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE
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| UART_CONFIG_PAR_NONE));
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MAP_UARTFlowControlSet(config->base, UART_FLOWCONTROL_NONE);
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/* Re-disable the FIFOs: */
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MAP_UARTFIFODisable(config->base);
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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/* Clear any pending UART RX interrupts: */
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MAP_UARTIntClear(config->base, UART_INT_RX);
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config->irq_config_func(dev);
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/* Fill the tx fifo, so Zephyr console & shell subsystems get "primed"
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* with first tx fifo empty interrupt when they first call
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* uart_irq_tx_enable().
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*/
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MAP_UARTCharPutNonBlocking(config->base, PRIME_CHAR);
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#endif
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return 0;
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}
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static int uart_cc32xx_poll_in(const struct device *dev, unsigned char *c)
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{
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const struct uart_cc32xx_dev_config *config = dev->config;
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if (MAP_UARTCharsAvail(config->base)) {
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*c = MAP_UARTCharGetNonBlocking(config->base);
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} else {
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return (-1);
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}
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return 0;
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}
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static void uart_cc32xx_poll_out(const struct device *dev, unsigned char c)
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{
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const struct uart_cc32xx_dev_config *config = dev->config;
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MAP_UARTCharPut(config->base, c);
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}
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static int uart_cc32xx_err_check(const struct device *dev)
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{
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const struct uart_cc32xx_dev_config *config = dev->config;
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unsigned long cc32xx_errs = 0L;
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unsigned int z_err = 0U;
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cc32xx_errs = MAP_UARTRxErrorGet(config->base);
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/* Map cc32xx SDK uart.h defines to zephyr uart.h defines */
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z_err = ((cc32xx_errs & UART_RXERROR_OVERRUN) ?
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UART_ERROR_OVERRUN : 0) |
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((cc32xx_errs & UART_RXERROR_BREAK) ? UART_BREAK : 0) |
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((cc32xx_errs & UART_RXERROR_PARITY) ? UART_ERROR_PARITY : 0) |
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((cc32xx_errs & UART_RXERROR_FRAMING) ? UART_ERROR_FRAMING : 0);
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MAP_UARTRxErrorClear(config->base);
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return (int)z_err;
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static int uart_cc32xx_fifo_fill(const struct device *dev,
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const uint8_t *tx_data,
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int size)
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{
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const struct uart_cc32xx_dev_config *config = dev->config;
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unsigned int num_tx = 0U;
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while ((size - num_tx) > 0) {
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/* Send a character */
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if (MAP_UARTCharPutNonBlocking(config->base, tx_data[num_tx])) {
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num_tx++;
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} else {
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break;
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}
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}
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return (int)num_tx;
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}
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static int uart_cc32xx_fifo_read(const struct device *dev, uint8_t *rx_data,
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const int size)
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{
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const struct uart_cc32xx_dev_config *config = dev->config;
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unsigned int num_rx = 0U;
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while (((size - num_rx) > 0) &&
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MAP_UARTCharsAvail(config->base)) {
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/* Receive a character */
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rx_data[num_rx++] =
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MAP_UARTCharGetNonBlocking(config->base);
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}
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return num_rx;
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}
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static void uart_cc32xx_irq_tx_enable(const struct device *dev)
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{
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const struct uart_cc32xx_dev_config *config = dev->config;
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MAP_UARTIntEnable(config->base, UART_INT_TX);
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}
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static void uart_cc32xx_irq_tx_disable(const struct device *dev)
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{
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const struct uart_cc32xx_dev_config *config = dev->config;
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MAP_UARTIntDisable(config->base, UART_INT_TX);
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}
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static int uart_cc32xx_irq_tx_ready(const struct device *dev)
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{
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const struct uart_cc32xx_dev_config *config = dev->config;
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unsigned int int_status;
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int_status = MAP_UARTIntStatus(config->base, 1);
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return (int_status & UART_INT_TX);
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}
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static void uart_cc32xx_irq_rx_enable(const struct device *dev)
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{
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const struct uart_cc32xx_dev_config *config = dev->config;
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/* FIFOs are left disabled from reset, so UART_INT_RT flag not used. */
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MAP_UARTIntEnable(config->base, UART_INT_RX);
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}
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static void uart_cc32xx_irq_rx_disable(const struct device *dev)
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{
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const struct uart_cc32xx_dev_config *config = dev->config;
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MAP_UARTIntDisable(config->base, UART_INT_RX);
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}
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static int uart_cc32xx_irq_tx_complete(const struct device *dev)
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{
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const struct uart_cc32xx_dev_config *config = dev->config;
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return (!MAP_UARTBusy(config->base));
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}
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static int uart_cc32xx_irq_rx_ready(const struct device *dev)
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{
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const struct uart_cc32xx_dev_config *config = dev->config;
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unsigned int int_status;
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int_status = MAP_UARTIntStatus(config->base, 1);
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return (int_status & UART_INT_RX);
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}
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static void uart_cc32xx_irq_err_enable(const struct device *dev)
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{
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/* Not yet used in zephyr */
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}
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static void uart_cc32xx_irq_err_disable(const struct device *dev)
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{
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/* Not yet used in zephyr */
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}
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static int uart_cc32xx_irq_is_pending(const struct device *dev)
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{
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const struct uart_cc32xx_dev_config *config = dev->config;
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unsigned int int_status;
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int_status = MAP_UARTIntStatus(config->base, 1);
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return (int_status & (UART_INT_TX | UART_INT_RX));
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}
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static int uart_cc32xx_irq_update(const struct device *dev)
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{
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return 1;
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}
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static void uart_cc32xx_irq_callback_set(const struct device *dev,
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uart_irq_callback_user_data_t cb,
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void *cb_data)
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{
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struct uart_cc32xx_dev_data_t * const dev_data = dev->data;
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dev_data->cb = cb;
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dev_data->cb_data = cb_data;
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}
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/**
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* @brief Interrupt service routine.
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*
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* This simply calls the callback function, if one exists.
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*
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* Note: CC32XX UART Tx interrupts when ready to send; Rx interrupts when char
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* received.
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*
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* @param arg Argument to ISR.
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*/
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static void uart_cc32xx_isr(const struct device *dev)
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{
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const struct uart_cc32xx_dev_config *config = dev->config;
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struct uart_cc32xx_dev_data_t * const dev_data = dev->data;
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unsigned long intStatus = MAP_UARTIntStatus(config->base, 1);
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if (dev_data->cb) {
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dev_data->cb(dev, dev_data->cb_data);
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}
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/*
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* RX/TX interrupt should have been implicitly cleared by Zephyr UART
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* clients calling uart_fifo_read() or uart_fifo_write().
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* Still, clear any error interrupts here, as they're not yet handled.
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*/
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MAP_UARTIntClear(config->base,
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intStatus & ~(UART_INT_RX | UART_INT_TX));
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}
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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static const struct uart_driver_api uart_cc32xx_driver_api = {
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.poll_in = uart_cc32xx_poll_in,
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.poll_out = uart_cc32xx_poll_out,
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.err_check = uart_cc32xx_err_check,
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.fifo_fill = uart_cc32xx_fifo_fill,
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.fifo_read = uart_cc32xx_fifo_read,
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.irq_tx_enable = uart_cc32xx_irq_tx_enable,
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.irq_tx_disable = uart_cc32xx_irq_tx_disable,
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.irq_tx_ready = uart_cc32xx_irq_tx_ready,
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.irq_rx_enable = uart_cc32xx_irq_rx_enable,
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.irq_rx_disable = uart_cc32xx_irq_rx_disable,
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.irq_tx_complete = uart_cc32xx_irq_tx_complete,
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.irq_rx_ready = uart_cc32xx_irq_rx_ready,
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.irq_err_enable = uart_cc32xx_irq_err_enable,
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.irq_err_disable = uart_cc32xx_irq_err_disable,
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.irq_is_pending = uart_cc32xx_irq_is_pending,
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.irq_update = uart_cc32xx_irq_update,
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.irq_callback_set = uart_cc32xx_irq_callback_set,
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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};
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#define UART_32XX_DEVICE(idx) \
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PINCTRL_DT_INST_DEFINE(idx); \
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IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, \
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(static void uart_cc32xx_cfg_func_##idx(const struct device *dev) \
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{ \
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IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, ( \
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IRQ_CONNECT(DT_INST_IRQN(idx), \
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DT_INST_IRQ(idx, priority), \
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uart_cc32xx_isr, DEVICE_DT_INST_GET(idx), \
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0); \
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irq_enable(DT_INST_IRQN(idx))) \
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); \
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})); \
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static const struct uart_cc32xx_dev_config uart_cc32xx_dev_cfg_##idx = { \
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.base = DT_INST_REG_ADDR(idx), \
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.sys_clk_freq = DT_INST_PROP_BY_PHANDLE(idx, clocks, clock_frequency),\
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \
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IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, \
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(.irq_config_func = uart_cc32xx_cfg_func_##idx,)) \
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}; \
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static struct uart_cc32xx_dev_data_t uart_cc32xx_dev_data_##idx = { \
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.prcm = PRCM_UARTA##idx, \
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.baud_rate = DT_INST_PROP(idx, current_speed), \
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IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, (.cb = NULL,)) \
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}; \
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DEVICE_DT_INST_DEFINE(idx, uart_cc32xx_init, \
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NULL, &uart_cc32xx_dev_data_##idx, \
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&uart_cc32xx_dev_cfg_##idx, \
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PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \
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(void *)&uart_cc32xx_driver_api); \
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DT_INST_FOREACH_STATUS_OKAY(UART_32XX_DEVICE);
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