123 lines
4.2 KiB
Plaintext
123 lines
4.2 KiB
Plaintext
#nRF UART(E) instance configuration
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# Copyright (c) 2023 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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config UART_$(nrfx_uart_num)_INTERRUPT_DRIVEN
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bool "Interrupt support on port $(nrfx_uart_num)"
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depends on UART_INTERRUPT_DRIVEN
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select UART_ASYNC_TO_INT_DRIVEN_API if !UART_NRFX_UARTE_LEGACY_SHIM
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default y
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help
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This option enables UART interrupt support on port $(nrfx_uart_num).
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config UART_$(nrfx_uart_num)_ASYNC
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bool "Asynchronous API support on port $(nrfx_uart_num)"
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depends on UART_ASYNC_API && !UART_$(nrfx_uart_num)_INTERRUPT_DRIVEN
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default y
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help
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This option enables UART Asynchronous API support on port $(nrfx_uart_num).
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config UART_$(nrfx_uart_num)_ENHANCED_POLL_OUT
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bool "Efficient poll out on port $(nrfx_uart_num)"
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depends on !SOC_SERIES_NRF54LX
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default y
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depends on HAS_HW_NRF_UARTE$(nrfx_uart_num)
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depends on HAS_HW_NRF_PPI || HAS_HW_NRF_DPPIC
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select NRFX_PPI if HAS_HW_NRF_PPI
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select NRFX_DPPI if HAS_HW_NRF_DPPIC
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help
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When enabled, polling out does not trigger interrupt which stops TX.
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Feature uses a PPI channel.
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config NRFX_UARTE$(nrfx_uart_num)
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def_bool y if HAS_HW_NRF_UARTE$(nrfx_uart_num) && !UART_NRFX_UARTE_LEGACY_SHIM
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config UART_$(nrfx_uart_num)_NRF_PARITY_BIT
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bool "Parity bit"
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help
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Enable parity bit.
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config UART_$(nrfx_uart_num)_NRF_TX_BUFFER_SIZE
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int "Size of RAM buffer"
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depends on HAS_HW_NRF_UARTE$(nrfx_uart_num)
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depends on UART_NRFX_UARTE_LEGACY_SHIM
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range 1 65535
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default 32
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help
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Size of the transmit buffer for API function: fifo_fill.
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This value is limited by range of TXD.MAXCNT register for
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particular SoC.
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config UART_$(nrfx_uart_num)_NRF_HW_ASYNC
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bool "Use hardware RX byte counting"
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depends on HAS_HW_NRF_UARTE$(nrfx_uart_num)
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depends on UART_ASYNC_API
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depends on UART_NRFX_UARTE_LEGACY_SHIM
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select NRFX_PPI if HAS_HW_NRF_PPI
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select NRFX_DPPI if HAS_HW_NRF_DPPIC
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help
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If default driver uses interrupts to count incoming bytes, it is possible
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that with higher speeds and/or high cpu load some data can be lost.
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It is recommended to use hardware byte counting in such scenarios.
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Hardware RX byte counting requires timer instance and one PPI channel.
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config UART_$(nrfx_uart_num)_NRF_ASYNC_LOW_POWER
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bool "Low power mode"
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depends on HAS_HW_NRF_UARTE$(nrfx_uart_num)
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depends on UART_ASYNC_API
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depends on UART_NRFX_UARTE_LEGACY_SHIM
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help
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When enabled, UARTE is enabled before each TX or RX usage and disabled
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when not used. Disabling UARTE while in idle allows to achieve lowest
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power consumption. It is only feasible if receiver is not always on.
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config UART_$(nrfx_uart_num)_NRF_HW_ASYNC_TIMER
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int "Timer instance"
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depends on UART_$(nrfx_uart_num)_NRF_HW_ASYNC
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config UART_$(nrfx_uart_num)_TX_CACHE_SIZE
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int "TX cache buffer size"
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depends on !UART_NRFX_UARTE_LEGACY_SHIM
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default 8
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help
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For UARTE, TX cache buffer is used when provided TX buffer is not located
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in memory which can be used by the EasyDMA.
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config UART_$(nrfx_uart_num)_RX_CACHE_SIZE
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int "RX cache buffer size"
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depends on !UART_NRFX_UARTE_LEGACY_SHIM
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default 32 if $(dt_nodelabel_has_compat,ram3x,$(DT_COMPAT_MMIO_SRAM))
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default 5
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range 5 255
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help
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For UARTE, RX cache buffer is used when provided RX buffer is not located
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in memory which can be used by the EasyDMA. It is also used to store
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flushed data.
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config UART_$(nrfx_uart_num)_A2I_RX_SIZE
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depends on !UART_NRFX_UARTE_LEGACY_SHIM
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int "Asynchronous to interrupt driven adaptation layer RX buffer size"
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default 64 if UART_$(nrfx_uart_num)_INTERRUPT_DRIVEN
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default 0
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help
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Amount of space dedicated for RX. It is divided into chunks with some
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amount of that space used for control data.
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config UART_$(nrfx_uart_num)_A2I_RX_BUF_COUNT
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depends on !UART_NRFX_UARTE_LEGACY_SHIM
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int "Asynchronous to interrupt driven adaptation layer RX buffer count"
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default 8 if UART_$(nrfx_uart_num)_INTERRUPT_DRIVEN
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default 0
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help
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Number of chunks into RX space is divided.
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config UART_$(nrfx_uart_num)_GPIO_MANAGEMENT
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bool "GPIO management on port $(nrfx_uart_num)"
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depends on PM_DEVICE
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default y
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help
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If enabled, the driver will configure the GPIOs used by the uart to
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their default configuration when device is powered down. The GPIOs
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will be configured back to correct state when UART is powered up.
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