96 lines
2.0 KiB
C
96 lines
2.0 KiB
C
/*
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*
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* Copyright (c) 2018 Ilya Tagunov
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_rcc.h>
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#include <stm32_ll_utils.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include "clock_stm32_ll_common.h"
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#if defined(STM32_PLL_ENABLED)
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/* Macros to fill up multiplication and division factors values */
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#define z_pll_mul(v) LL_RCC_PLL_MUL_ ## v
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#define pll_mul(v) z_pll_mul(v)
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#define z_pll_div(v) LL_RCC_PLL_DIV_ ## v
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#define pll_div(v) z_pll_div(v)
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/**
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* @brief Return PLL source
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*/
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__unused
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static uint32_t get_pll_source(void)
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{
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/* Configure PLL source */
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if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
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return LL_RCC_PLLSOURCE_HSI;
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} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
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return LL_RCC_PLLSOURCE_HSE;
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}
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__ASSERT(0, "Invalid source");
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return 0;
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}
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/**
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* @brief get the pll source frequency
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*/
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__unused
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uint32_t get_pllsrc_frequency(void)
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{
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if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
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return STM32_HSI_FREQ;
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} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
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return STM32_HSE_FREQ;
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}
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__ASSERT(0, "Invalid source");
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return 0;
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}
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/**
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* @brief Set up pll configuration
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*/
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__unused
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void config_pll_sysclock(void)
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{
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LL_RCC_PLL_ConfigDomain_SYS(get_pll_source(),
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pll_mul(STM32_PLL_MULTIPLIER),
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pll_div(STM32_PLL_DIVISOR));
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}
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/**
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* @brief Return pllout frequency
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*/
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__unused
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uint32_t get_pllout_frequency(void)
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{
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return __LL_RCC_CALC_PLLCLK_FREQ(get_pllsrc_frequency(),
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pll_mul(STM32_PLL_MULTIPLIER),
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pll_div(STM32_PLL_DIVISOR));
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}
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#endif /* defined(STM32_PLL_ENABLED) */
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/**
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* @brief Activate default clocks
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*/
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void config_enable_default_clocks(void)
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{
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#if defined(CONFIG_EXTI_STM32) || defined(CONFIG_USB_DC_STM32) || \
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(defined(CONFIG_SOC_SERIES_STM32L0X) && \
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defined(CONFIG_ENTROPY_STM32_RNG))
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/* Enable System Configuration Controller clock. */
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG);
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#endif
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}
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