530 lines
14 KiB
Plaintext
530 lines
14 KiB
Plaintext
/*
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* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <freq.h>
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#include <xtensa/xtensa.dtsi>
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#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/clock/esp32s3_clock.h>
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#include <zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h>
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#include <dt-bindings/pinctrl/esp32s3-pinctrl.h>
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/ {
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aliases {
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die-temp0 = &coretemp;
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};
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chosen {
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zephyr,canbus = &twai;
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zephyr,entropy = &trng0;
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zephyr,flash-controller = &flash;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "espressif,xtensa-lx7";
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reg = <0>;
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cpu-power-states = <&light_sleep &deep_sleep>;
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clock-source = <ESP32_CPU_CLK_SRC_PLL>;
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clock-frequency = <DT_FREQ_M(240)>;
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xtal-freq = <DT_FREQ_M(40)>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "espressif,xtensa-lx7";
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reg = <1>;
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clock-source = <ESP32_CPU_CLK_SRC_PLL>;
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clock-frequency = <DT_FREQ_M(240)>;
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xtal-freq = <DT_FREQ_M(40)>;
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};
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power-states {
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light_sleep: light_sleep {
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compatible = "zephyr,power-state";
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power-state-name = "standby";
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min-residency-us = <200>;
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exit-latency-us = <133>;
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};
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deep_sleep: deep_sleep {
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compatible = "zephyr,power-state";
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power-state-name = "soft-off";
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min-residency-us = <2000>;
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exit-latency-us = <382>;
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};
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};
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};
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wifi: wifi {
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compatible = "espressif,esp32-wifi";
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status = "disabled";
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};
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esp32_bt_hci: esp32_bt_hci {
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compatible = "espressif,esp32-bt-hci";
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status = "disabled";
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};
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pinctrl: pin-controller {
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compatible = "espressif,esp32-pinctrl";
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status = "okay";
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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sram0: memory@3fc88000 {
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compatible = "mmio-sram";
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reg = <0x3fc88000 0x77FFF>;
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};
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ipmmem0: memory@3fcbd000 {
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compatible = "mmio-sram";
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reg = <0x3fcbd000 0x400>;
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};
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shm0: memory@3fcbd400 {
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compatible = "mmio-sram";
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reg = <0x3fcbd400 0x4000>;
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};
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intc: interrupt-controller@600c2000 {
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#interrupt-cells = <3>;
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compatible = "espressif,esp32-intc";
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interrupt-controller;
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reg = <0x600c2000 0x1000>;
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status = "okay";
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};
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rtc: rtc@60021000 {
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compatible = "espressif,esp32-rtc";
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reg = <0x60021000 0x2000>;
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fast-clk-src = <ESP32_RTC_FAST_CLK_SRC_RC_FAST>;
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slow-clk-src = <ESP32_RTC_SLOW_CLK_SRC_RC_SLOW>;
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#clock-cells = <1>;
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status = "okay";
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};
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xt_wdt: xt_wdt@60021004 {
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compatible = "espressif,esp32-xt-wdt";
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reg = <0x60021004 0x4>;
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clocks = <&rtc ESP32_MODULE_MAX>;
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interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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status = "disabled";
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};
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rtc_timer: rtc_timer@60008004 {
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reg = <0x60008004 0xC>;
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compatible = "espressif,esp32-rtc-timer";
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clocks = <&rtc ESP32_MODULE_MAX>;
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interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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status = "disabled";
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};
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flash: flash-controller@60002000 {
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compatible = "espressif,esp32-flash-controller";
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reg = <0x60002000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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reg = <0 0x800000>;
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erase-block-size = <4096>;
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write-block-size = <4>;
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/* Flash size is specified in SOC/SIP dtsi */
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};
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};
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psram0: psram@3c000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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/* PSRAM size is specified in SOC/SIP dtsi */
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reg = <0x3c000000 DT_SIZE_M(2)>;
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status = "disabled";
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};
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ipm0: ipm@3fcc1400 {
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compatible = "espressif,esp32-ipm";
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reg = <0x3fcc1400 0x8>;
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status = "disabled";
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shared-memory = <&ipmmem0>;
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shared-memory-size = <0x400>;
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interrupts =
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<FROM_CPU_INTR0_SOURCE IRQ_DEFAULT_PRIORITY 0>,
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<FROM_CPU_INTR1_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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};
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mbox0: mbox@3fcc1408 {
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compatible = "espressif,mbox-esp32";
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reg = <0x3fcc1408 0x8>;
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status = "disabled";
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shared-memory = <&ipmmem0>;
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shared-memory-size = <0x400>;
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interrupts =
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<FROM_CPU_INTR0_SOURCE IRQ_DEFAULT_PRIORITY 0>,
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<FROM_CPU_INTR1_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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#mbox-cells = <1>;
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};
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uart0: uart@60000000 {
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compatible = "espressif,esp32-uart";
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reg = <0x60000000 0x1000>;
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interrupts = <UART0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_UART0_MODULE>;
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status = "disabled";
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};
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uart1: uart@60010000 {
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compatible = "espressif,esp32-uart";
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reg = <0x60010000 0x1000>;
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interrupts = <UART1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_UART1_MODULE>;
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status = "disabled";
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};
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uart2: uart@6002e000 {
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compatible = "espressif,esp32-uart";
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reg = <0x6002e000 0x1000>;
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interrupts = <UART2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_UART2_MODULE>;
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status = "disabled";
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};
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gpio: gpio {
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compatible = "simple-bus";
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gpio-map-mask = <0xffffffe0 0xffffffc0>;
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gpio-map-pass-thru = <0x1f 0x3f>;
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gpio-map = <
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0x00 0x0 &gpio0 0x0 0x0
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0x20 0x0 &gpio1 0x0 0x0
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>;
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#gpio-cells = <2>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio0: gpio@60004000 {
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compatible = "espressif,esp32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x60004000 0x800>;
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interrupts = <GPIO_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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/* Maximum available pins (per port)
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* Actual occupied pins are specified
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* on part number dtsi level, using
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* the `gpio-reserved-ranges` property.
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*/
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ngpios = <32>; /* 0..31 */
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};
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gpio1: gpio@60004800 {
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compatible = "espressif,esp32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x60004800 0x800>;
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interrupts = <GPIO_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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ngpios = <22>; /* 32..53 */
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};
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};
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touch: touch@6000885c {
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compatible = "espressif,esp32-touch";
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reg = <0x6000885c 0x88 0x60008908 0x18>;
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interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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status = "disabled";
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};
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i2c0: i2c@60013000 {
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compatible = "espressif,esp32-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x60013000 DT_SIZE_K(4)>;
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interrupts = <I2C_EXT0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_I2C0_MODULE>;
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status = "disabled";
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};
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i2c1: i2c@60027000 {
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compatible = "espressif,esp32-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x60027000 DT_SIZE_K(4)>;
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interrupts = <I2C_EXT1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_I2C1_MODULE>;
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status = "disabled";
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};
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i2s0: i2s@6000f000 {
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compatible = "espressif,esp32-i2s";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x6000f000 0x1000>;
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interrupts = <I2S0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_I2S0_MODULE>;
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dmas = <&dma 2>, <&dma 3>;
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dma-names = "rx", "tx";
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unit = <0>;
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status = "disabled";
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};
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i2s1: i2s@6002d000 {
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compatible = "espressif,esp32-i2s";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x6002d000 0x1000>;
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interrupts = <I2S1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_I2S1_MODULE>;
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dmas = <&dma 4>, <&dma 5>;
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dma-names = "rx", "tx";
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unit = <1>;
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status = "disabled";
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};
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spi2: spi@60024000 {
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compatible = "espressif,esp32-spi";
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reg = <0x60024000 DT_SIZE_K(4)>;
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interrupts = <SPI2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_SPI2_MODULE>;
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dma-clk = <ESP32_GDMA_MODULE>;
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dma-host = <0>;
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status = "disabled";
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};
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spi3: spi@60025000 {
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compatible = "espressif,esp32-spi";
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reg = <0x60025000 DT_SIZE_K(4)>;
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interrupts = <SPI3_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_SPI3_MODULE>;
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dma-clk = <ESP32_GDMA_MODULE>;
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dma-host = <1>;
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status = "disabled";
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};
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coretemp: coretemp@60008800 {
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compatible = "espressif,esp32-temp";
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friendly-name = "coretemp";
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reg = <0x60008800 0x4>;
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status = "disabled";
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};
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adc0: adc@60040000 {
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compatible = "espressif,esp32-adc";
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reg = <0x60040000 4>;
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unit = <1>;
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channel-count = <10>;
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#io-channel-cells = <1>;
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status = "disabled";
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};
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adc1: adc@60040004 {
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compatible = "espressif,esp32-adc";
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reg = <0x60040004 4>;
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unit = <2>;
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channel-count = <10>;
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#io-channel-cells = <1>;
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status = "disabled";
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};
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twai: can@6002b000 {
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compatible = "espressif,esp32-twai";
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reg = <0x6002b000 DT_SIZE_K(4)>;
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interrupts = <TWAI_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_TWAI_MODULE>;
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status = "disabled";
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};
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lcd_cam: lcd_cam@60041000 {
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compatible = "espressif,esp32-lcd-cam";
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reg = <0x60041000 DT_SIZE_K(4)>;
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clocks = <&rtc ESP32_LCD_CAM_MODULE>;
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interrupts = <LCD_CAM_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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status = "disabled";
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};
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usb_serial: uart@60038000 {
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compatible = "espressif,esp32-usb-serial";
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reg = <0x60038000 DT_SIZE_K(4)>;
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status = "disabled";
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interrupts = <USB_SERIAL_JTAG_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_USB_MODULE>;
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};
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timer0: counter@6001f000 {
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compatible = "espressif,esp32-timer";
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reg = <0x6001f000 DT_SIZE_K(4)>;
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group = <0>;
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index = <0>;
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interrupts = <TG0_T0_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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status = "disabled";
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};
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timer1: counter@6001f024 {
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compatible = "espressif,esp32-timer";
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reg = <0x6001f024 DT_SIZE_K(4)>;
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group = <0>;
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index = <1>;
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interrupts = <TG0_T1_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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status = "disabled";
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};
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timer2: counter@60020000 {
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compatible = "espressif,esp32-timer";
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reg = <0x60020000 DT_SIZE_K(4)>;
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group = <1>;
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index = <0>;
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interrupts = <TG1_T0_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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status = "disabled";
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};
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timer3: counter@60020024 {
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compatible = "espressif,esp32-timer";
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reg = <0x60020024 DT_SIZE_K(4)>;
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group = <1>;
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index = <1>;
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interrupts = <TG1_T1_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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};
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wdt0: watchdog@6001f048 {
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compatible = "espressif,esp32-watchdog";
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reg = <0x6001f048 0x20>;
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interrupts = <TG0_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_TIMG0_MODULE>;
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status = "disabled";
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};
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wdt1: watchdog@60020048 {
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compatible = "espressif,esp32-watchdog";
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reg = <0x60020048 0x20>;
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interrupts = <TG1_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_TIMG1_MODULE>;
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status = "disabled";
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};
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trng0: trng@6003507c {
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compatible = "espressif,esp32-trng";
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reg = <0x6003507c 0x4>;
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status = "disabled";
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};
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ledc0: ledc@60019000 {
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compatible = "espressif,esp32-ledc";
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#pwm-cells = <3>;
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reg = <0x60019000 DT_SIZE_K(4)>;
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clocks = <&rtc ESP32_LEDC_MODULE>;
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status = "disabled";
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};
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mcpwm0: mcpwm@6001e000 {
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compatible = "espressif,esp32-mcpwm";
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reg = <0x6001e000 DT_SIZE_K(4)>;
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interrupts = <PWM0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_PWM0_MODULE>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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mcpwm1: mcpwm@6002c000 {
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compatible = "espressif,esp32-mcpwm";
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reg = <0x6002c000 DT_SIZE_K(4)>;
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interrupts = <PWM1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_PWM1_MODULE>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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pcnt: pcnt@60017000 {
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compatible = "espressif,esp32-pcnt";
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reg = <0x60017000 DT_SIZE_K(4)>;
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interrupts = <PCNT_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_PCNT_MODULE>;
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status = "disabled";
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};
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dma: dma@6003f000 {
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compatible = "espressif,esp32-gdma";
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reg = <0x6003f000 DT_SIZE_K(4)>;
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#dma-cells = <1>;
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interrupts =
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<DMA_IN_CH0_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>,
|
|
<DMA_OUT_CH0_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>,
|
|
<DMA_IN_CH1_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>,
|
|
<DMA_OUT_CH1_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>,
|
|
<DMA_IN_CH2_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>,
|
|
<DMA_OUT_CH2_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>,
|
|
<DMA_IN_CH3_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>,
|
|
<DMA_OUT_CH3_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>,
|
|
<DMA_IN_CH4_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>,
|
|
<DMA_OUT_CH4_INTR_SOURCE IRQ_DEFAULT_PRIORITY ESP_INTR_FLAG_SHARED>;
|
|
interrupt-parent = <&intc>;
|
|
clocks = <&rtc ESP32_GDMA_MODULE>;
|
|
dma-channels = <10>;
|
|
dma-buf-addr-alignment = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhc: sdhc@60028000 {
|
|
compatible = "espressif,esp32-sdhc";
|
|
reg = <0x60028000 0x1000>;
|
|
interrupts = <SDIO_HOST_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
|
|
interrupt-parent = <&intc>;
|
|
clocks = <&rtc ESP32_SDMMC_MODULE>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
sdhc0: sdhc@0 {
|
|
compatible = "espressif,esp32-sdhc-slot";
|
|
reg = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhc1: sdhc@1 {
|
|
compatible = "espressif,esp32-sdhc-slot";
|
|
reg = <1>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
};
|