06d222d16d
On mcu with Data Cache, when it is enabled (CONFIG_DCACHE=y), the DCACHE must be flushed after the NMI loop to trig all the irq, else the last one is missing. Signed-off-by: Francois Ramu <francois.ramu@st.com> |
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arm | ||
arm64 | ||
common/semihost | ||
x86 | ||
xtensa_asm2 |